1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright (C) 2025 Altera Corporation 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Altera SoCFPGA ECC Manager 9 10maintainers: 11 - Matthew Gerlach <matthew.gerlach@altera.com> 12 13description: 14 This binding describes the device tree nodes required for the Altera SoCFPGA 15 ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip 16 families. 17 18properties: 19 20 compatible: 21 oneOf: 22 - items: 23 - const: altr,socfpga-s10-ecc-manager 24 - const: altr,socfpga-a10-ecc-manager 25 - const: altr,socfpga-a10-ecc-manager 26 - const: altr,socfpga-ecc-manager 27 28 "#address-cells": 29 const: 1 30 31 "#size-cells": 32 const: 1 33 34 interrupts: 35 minItems: 1 36 maxItems: 2 37 38 interrupt-controller: true 39 40 "#interrupt-cells": 41 const: 2 42 43 ranges: true 44 45 altr,sysmgr-syscon: 46 $ref: /schemas/types.yaml#/definitions/phandle 47 description: phandle to Stratix10 System Manager Block with the ECC manager registers 48 49 sdramedac: 50 type: object 51 additionalProperties: false 52 53 properties: 54 compatible: 55 enum: 56 - altr,sdram-edac-a10 57 - altr,sdram-edac-s10 58 59 interrupts: 60 minItems: 1 61 maxItems: 2 62 63 altr,sdr-syscon: 64 $ref: /schemas/types.yaml#/definitions/phandle 65 description: phandle to SDRAM parent 66 67 required: 68 - compatible 69 - interrupts 70 - altr,sdr-syscon 71 72patternProperties: 73 "^ocram-ecc@[a-f0-9]+$": 74 type: object 75 additionalProperties: false 76 77 properties: 78 compatible: 79 oneOf: 80 - items: 81 - const: altr,socfpga-s10-ocram-ecc 82 - const: altr,socfpga-a10-ocram-ecc 83 - const: altr,socfpga-a10-ocram-ecc 84 - const: altr,socfpga-ocram-ecc 85 86 reg: 87 maxItems: 1 88 89 interrupts: 90 minItems: 1 91 maxItems: 2 92 93 iram: 94 $ref: /schemas/types.yaml#/definitions/phandle 95 description: phandle to OCRAM parent 96 97 altr,ecc-parent: 98 $ref: /schemas/types.yaml#/definitions/phandle 99 description: phandle to OCRAM parent 100 101 required: 102 - compatible 103 - reg 104 - interrupts 105 106 "^usb[0-9]-ecc@[a-f0-9]+$": 107 type: object 108 additionalProperties: false 109 110 properties: 111 compatible: 112 oneOf: 113 - items: 114 - const: altr,socfpga-s10-usb-ecc 115 - const: altr,socfpga-usb-ecc 116 - const: altr,socfpga-usb-ecc 117 118 reg: 119 maxItems: 1 120 121 interrupts: 122 minItems: 1 123 maxItems: 2 124 125 altr,ecc-parent: 126 $ref: /schemas/types.yaml#/definitions/phandle 127 description: phandle to USB parent 128 129 required: 130 - compatible 131 - reg 132 - interrupts 133 - altr,ecc-parent 134 135 "^emac[0-9]-[t,r]x-ecc@[a-f0-9]+$": 136 type: object 137 additionalProperties: false 138 139 properties: 140 compatible: 141 oneOf: 142 - items: 143 - const: altr,socfpga-s10-eth-mac-ecc 144 - const: altr,socfpga-eth-mac-ecc 145 - const: altr,socfpga-eth-mac-ecc 146 147 reg: 148 maxItems: 1 149 150 interrupts: 151 minItems: 1 152 maxItems: 2 153 154 altr,ecc-parent: 155 $ref: /schemas/types.yaml#/definitions/phandle 156 description: phandle to ethernet parent 157 158 required: 159 - compatible 160 - reg 161 - interrupts 162 - altr,ecc-parent 163 164 "^sdmmc[a-f]-ecc@[a-f0-9]+$": 165 type: object 166 additionalProperties: false 167 168 properties: 169 compatible: 170 oneOf: 171 - items: 172 - const: altr,socfpga-s10-sdmmc-ecc 173 - const: altr,socfpga-sdmmc-ecc 174 - const: altr,socfpga-sdmmc-ecc 175 176 reg: 177 maxItems: 1 178 179 interrupts: 180 minItems: 2 181 maxItems: 4 182 183 altr,ecc-parent: 184 $ref: /schemas/types.yaml#/definitions/phandle 185 description: phandle to SD/MMC parent 186 187 required: 188 - compatible 189 - reg 190 - interrupts 191 - altr,ecc-parent 192 193 "^l2-ecc@[a-f0-9]+$": 194 type: object 195 additionalProperties: false 196 197 properties: 198 compatible: 199 enum: 200 - altr,socfpga-a10-l2-ecc 201 - altr,socfpga-l2-ecc 202 203 reg: 204 maxItems: 1 205 206 interrupts: 207 maxItems: 2 208 209 required: 210 - compatible 211 - reg 212 - interrupts 213 214 "^dma-ecc@[a-f0-9]+$": 215 type: object 216 additionalProperties: false 217 218 properties: 219 compatible: 220 const: altr,socfpga-dma-ecc 221 reg: 222 maxItems: 1 223 224 interrupts: 225 maxItems: 2 226 227 altr,ecc-parent: 228 $ref: /schemas/types.yaml#/definitions/phandle 229 description: phandle to SD/MMC parent 230 231 required: 232 - compatible 233 - reg 234 - interrupts 235 - altr,ecc-parent 236 237if: 238 properties: 239 compatible: 240 contains: 241 const: altr,socfpga-ecc-manager 242then: 243 required: 244 - compatible 245 - "#address-cells" 246 - "#size-cells" 247 - ranges 248 249else: 250 required: 251 - compatible 252 - "#address-cells" 253 - "#size-cells" 254 - interrupts 255 - interrupt-controller 256 - "#interrupt-cells" 257 - ranges 258 - altr,sysmgr-syscon 259 260additionalProperties: false 261 262examples: 263 - | 264 #include <dt-bindings/interrupt-controller/arm-gic.h> 265 #include <dt-bindings/interrupt-controller/irq.h> 266 eccmgr { 267 compatible = "altr,socfpga-s10-ecc-manager", 268 "altr,socfpga-a10-ecc-manager"; 269 altr,sysmgr-syscon = <&sysmgr>; 270 #address-cells = <1>; 271 #size-cells = <1>; 272 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 ranges; 276 277 sdramedac { 278 compatible = "altr,sdram-edac-s10"; 279 altr,sdr-syscon = <&sdr>; 280 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 281 }; 282 283 ocram-ecc@ff8cc000 { 284 compatible = "altr,socfpga-s10-ocram-ecc", 285 "altr,socfpga-a10-ocram-ecc"; 286 reg = <0xff8cc000 0x100>; 287 altr,ecc-parent = <&ocram>; 288 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 289 }; 290 291 usb0-ecc@ff8c4000 { 292 compatible = "altr,socfpga-s10-usb-ecc", 293 "altr,socfpga-usb-ecc"; 294 reg = <0xff8c4000 0x100>; 295 altr,ecc-parent = <&usb0>; 296 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 297 }; 298 299 emac0-rx-ecc@ff8c0000 { 300 compatible = "altr,socfpga-s10-eth-mac-ecc", 301 "altr,socfpga-eth-mac-ecc"; 302 reg = <0xff8c0000 0x100>; 303 altr,ecc-parent = <&gmac0>; 304 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 305 }; 306 307 emac0-tx-ecc@ff8c0400 { 308 compatible = "altr,socfpga-s10-eth-mac-ecc", 309 "altr,socfpga-eth-mac-ecc"; 310 reg = <0xff8c0400 0x100>; 311 altr,ecc-parent = <&gmac0>; 312 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 313 }; 314 315 sdmmca-ecc@ff8c8c00 { 316 compatible = "altr,socfpga-s10-sdmmc-ecc", 317 "altr,socfpga-sdmmc-ecc"; 318 reg = <0xff8c8c00 0x100>; 319 altr,ecc-parent = <&mmc>; 320 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 321 <15 IRQ_TYPE_LEVEL_HIGH>; 322 }; 323 }; 324