Lines Matching +full:l2 +full:- +full:ecc
3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
7 * Copyright (c) 1994-1996 Mark Brinicombe.
69 /* The high-order byte is always the implementor */
88 /* On recent ARMs this byte holds the architecture and variant (sub-model) */
145 /* XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 */
165 #define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */
169 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID.
174 #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
223 * Post-ARM3 CP15 registers:
237 * 7 Cache/write-buffer Control
263 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
264 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
266 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
282 #define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */
295 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
315 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
317 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
318 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
319 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
323 #define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */
329 #define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */
330 #define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
331 #define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */
347 #define CPU_CT_CTYPE_WT 0 /* write-through */
348 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
390 #define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */
391 #define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */
394 #define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */
397 #define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */
398 #define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */
404 #define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */
407 ((((fsr) & (1 << 10)) >> (10 - 4))))
409 #define FSR_WNR (1 << 11) /* Write-not-Read access */
429 * +-------+-------------------------------------------------------+
432 * +-------+-------------------------------------------------------+