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/linux/drivers/mailbox/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
37 will be discovered and possibly managed at probe-time.
54 processer can write data in a channel, and set co-responding register
55 to raise interrupt to notice another processor, and it is allowed to
101 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
118 This driver provides support for inter-processor communication
119 between CPU cores and MCU processor on Some Rockchip SOCs.
207 module will be called mailbox-mpfs.
212 tristate "Microchip Inter-processor Communication (IPC) SBI driver"
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H A Dmailbox-mchp-ipc-sbi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip Inter-Processor communication (IPC) driver
5 * Copyright (c) 2021 - 2024 Microchip Technology Inc. All rights reserved.
19 #include <linux/dma-mapping.h>
21 #include <linux/mailbox/mchp-ipc.h>
44 * struct mchp_ipc_mbox_info - IPC probe message format
58 * struct mchp_ipc_init - IPC channel init message format
70 * struct mchp_ipc_status - IPC status message format
85 * struct mchp_ipc_sbi_msg - IPC SBI payload message
92 * ids to send/receive a message from an associated processor using
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/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Ddata-fabric.json4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
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/linux/Documentation/devicetree/bindings/powerpc/nintendo/
H A Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
34 1.b) The Processor Interface (PI) node
36 Represents the data and control interface between the main processor
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dandestech,plicsw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Andes machine-level software interrupt controller
12 controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
13 inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
15 generate machine-mode inter-processor interrupts through programming its
19 - Ben Zong-You Xie <ben717@andestech.com>
24 - enum:
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H A Dmarvell,mpic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
26 - description: main registers
27 - description: per-cpu registers
31 - description: |
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom-ipcc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
18 a case, the client would be Modem (client-id is 2) and the signal would be
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H A Daspeed,ast2700-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jammy Huang <jammy_huang@aspeedtech.com>
15 messages to each other. It is a hardware-based inter-processor communication
19 The mailbox's tx/rx are independent, meaning that one processor can send a
20 message while another processor is receiving a message simultaneously.
31 const: aspeed,ast2700-mailbox
35 - description: TX control register
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H A Daxiado,ax3005-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/axiado,ax3005-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishnakumar Kesavan <kkesavan@axiado.com>
11 - Prasad Bolisetty <pbolisetty@axiado.com>
12 - Swark Yang <syang@axiado.com>
15 The Axiado mailbox controller provides inter-processor communication
17 separate TX and RX register regions. Only the RX channels (channels 8-15)
18 generate interrupts; TX channels are purely poll/write-based.
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/linux/sound/soc/intel/avs/
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2021-2022 Intel Corporation
12 #include <linux/io-64-nonatomic-lo-hi.h>
45 /* SKL Intel HD Audio Inter-Processor Communication Registers */
57 /* CNL Intel HD Audio Inter-Processor Communication Registers */
72 /* MTL Intel HOST Inter-Processor Communication Registers */
115 #define AVS_FW_REG_BASE(adev) ((adev)->spec->hipc->sts_offset)
122 /* DSP -> HOST communication window */
124 /* HOST -> DSP communication window */
130 ((adev)->spec->sram->base_offset + \
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/linux/arch/arc/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
30 #include <asm/processor.h>
51 return -EINVAL; in arc_get_cpu_map()
54 return -EINVAL; in arc_get_cpu_map()
61 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
67 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
68 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
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/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_TW.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片組的主中
16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在這種模型裏面，IPI（Inter-Processor Interrupt）和CPU本地時鐘中斷直接發送到CPUINTC，
27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然後被HTVECINTC統一收集，再發送到LIOINTC，最後到達CPUINTC::
30 +-----+ +---------+ +-------+
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/linux/drivers/media/platform/mediatek/vcodec/encoder/
H A Dvenc_vpu_if.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * struct venc_vpu_inst - encoder VPU driver instance
23 * @id: the id of inter-processor interrupt
H A Dvenc_ipi_msg.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * enum venc_ipi_msg_id - message id between AP and VPU
17 * (ipi stands for inter-processor interrupt)
34 * struct venc_ap_ipi_msg_init - AP to VPU init cmd structure
49 * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure
71 * struct venc_ap_ipi_msg_enc - AP to VPU enc cmd structure
91 * struct venc_ap_ipi_msg_enc_ext - AP to SCP extended enc cmd structure
104 * struct venc_ap_ipi_msg_enc_ext_34 - AP to SCP extended enc cmd structure
128 * struct venc_ap_ipi_msg_deinit - AP to VPU deinit cmd structure
139 * enum venc_ipi_msg_status - VPU ack AP cmd status
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/linux/arch/mips/kernel/
H A Dsmp-up.c6 * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)
14 * Send inter-processor interrupt
58 return -ENOSYS; in up_cpu_disable()
/linux/Documentation/virt/kvm/devices/
H A Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
56 * Current processor priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
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/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,mdp3-rdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
24 - enum:
25 - mediatek,mt8183-mdp3-rdma
26 - mediatek,mt8188-mdp3-rdma
27 - mediatek,mt8195-mdp3-rdma
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/linux/Documentation/userspace-api/media/
H A Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
52 **Digital Signal Processor**
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
72 together make a larger user-facing functional peripheral. For
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
84 like sub-device hardware components.
86 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
108 **Image Signal Processor**
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/linux/drivers/net/ethernet/intel/libeth/
H A Dxsk.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * libeth_xsk_buff_free_slow - free an XSk Rx buffer
38 xsk_buff_free(&xdp->base); in libeth_xsk_buff_free_slow()
43 * libeth_xsk_buff_add_frag - add frag to XSk Rx buffer
56 if (!xsk_buff_add_frag(&head->base, &xdp->base)) in libeth_xsk_buff_add_frag()
70 * libeth_xsk_buff_stats_frags - update onstack RQ stats with XSk frags info
85 * __libeth_xsk_run_prog_slow - process the non-``XDP_REDIRECT`` verdicts
93 * it is processed inline. The rest goes here for out-of-line processing,
104 xsk_buff_free(&xdp->base); in __libeth_xsk_run_prog_slow()
120 * libeth_xsk_prog_exception - handle XDP prog exceptions on XSk
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/linux/arch/alpha/include/asm/
H A Dcore_t2.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * memory controller and PCI access for the SABLE-based systems.
27 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
87 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
90 * +--------------+ 3 8000 0000
92 * +--------------+ 3 8100 0000
94 * +--------------+ 3 8200 0000
96 * +--------------+ 3 8300 0000
98 * +--------------+ 3 8400 0000
100 * +--------------+ 3 8700 0000
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/linux/arch/arm64/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <linux/irqchip/arm-gic-v3.h>
51 #include <asm/processor.h>
78 #define get_ipi_desc(__cpu, __ipi) (per_cpu_ptr(&pcpu_ipi_desc, __cpu)->descs[__ipi])
92 return -ENOSYS; in op_cpu_kill()
105 if (ops->cpu_boot) in boot_secondary()
106 return ops->cpu_boot(cpu); in boot_secondary()
108 return -EOPNOTSUPP; in boot_secondary()
128 if (ret != -EPERM) in __cpu_up()
164 pr_crit("CPU%u: does not support 52-bit VAs\n", cpu); in __cpu_up()
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/linux/arch/parisc/include/asm/
H A Dpgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <asm-generic/pgtable-nopud.h>
10 #include <asm-generic/pgtable-nopmd.h>
17 * we simulate an x86-style page table for the linux mm code
23 #include <asm/processor.h>
27 * systems, only one PxTLB inter processor broadcast can be active at any one
58 mtsp(mm->context.space_id, SR_TEMP1); in purge_tlb_entries()
107 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
114 #define PMD_MASK (~(PMD_SIZE-1))
115 #define BITS_PER_PMD (PAGE_SHIFT + PMD_TABLE_ORDER - BITS_PER_PMD_ENTRY)
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/linux/Documentation/arch/arm/
H A Dcluster-pm-race-avoidance.rst2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
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/linux/arch/xtensa/kernel/
H A Dsmp.c8 * Copyright (C) 2008 - 2013 Tensilica Inc.
53 /* IPI (Inter Process Interrupt) */
117 static int boot_secondary_processors = 1; /* Set with xt-gdb via .xt-gdb */
146 current->active_mm = mm; in secondary_start_kernel()
174 pr_debug("%s: cpu: %d, run_stall_mask: %lx ---> %lx\n", in mx_cpu_start()
184 pr_debug("%s: cpu: %d, run_stall_mask: %lx ---> %lx\n", in mx_cpu_stop()
228 return -EIO; in boot_secondary()
253 ret = -EIO; in __cpu_up()
265 * __cpu_disable runs on the processor to be shutdown.
284 * OK - migrate IRQs away from this CPU in __cpu_disable()
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/linux/tools/include/uapi/linux/
H A Dio_uring.h1 /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
56 __u32 poll32_events; /* word-reversed for BE */
109 * If sqe->file_index is set to this for opcodes that instantiate a new
112 * in. The picked direct descriptor will be returned in cqe->res, or -ENFILE
128 * sqe->flags
140 /* select buffer from sqe->buf_group */
160 * than force an inter-processor interrupt reschedule. This avoids interrupting
262 * sqe->uring_cmd_flags top 8bits aren't available for userspace
264 * along with setting sqe->buf_index.
271 * sqe->fsync_flags
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