Lines Matching +full:inter +full:- +full:processor
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
24 - enum:
25 - mediatek,mt8183-mdp3-rdma
26 - mediatek,mt8188-mdp3-rdma
27 - mediatek,mt8195-mdp3-rdma
28 - mediatek,mt8195-vdo1-rdma
29 - items:
30 - const: mediatek,mt8188-vdo1-rdma
31 - const: mediatek,mt8195-vdo1-rdma
36 mediatek,gce-client-reg:
37 $ref: /schemas/types.yaml#/definitions/phandle-array
40 - description: phandle of GCE
41 - description: GCE subsys id
42 - description: register offset
43 - description: register size
46 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
48 mediatek,gce-events:
52 include/dt-bindings/gce/<chip>-gce.h of each chips.
53 $ref: /schemas/types.yaml#/definitions/uint32-array
58 Phandle to the System Control Processor (SCP) used for initializing
60 VPU and to install Inter-Processor Interrupt handlers to control
63 power-domains:
68 - description: RDMA clock
69 - description: RSZ clock
77 - description: used for 1st data pipe from RDMA
78 - description: used for 2nd data pipe from RDMA
79 - description: used for 3rd data pipe from RDMA
80 - description: used for 4th data pipe from RDMA
81 - description: used for the data pipe from SPLIT
87 '#dma-cells':
91 - compatible
92 - reg
93 - mediatek,gce-client-reg
94 - power-domains
95 - clocks
96 - iommus
97 - '#dma-cells'
100 - if:
104 const: mediatek,mt8183-mdp3-rdma
115 - mboxes
116 - mediatek,gce-events
118 - if:
122 const: mediatek,mt8195-mdp3-rdma
133 - mediatek,gce-events
135 - if:
139 const: mediatek,mt8195-vdo1-rdma
149 - |
150 #include <dt-bindings/clock/mt8183-clk.h>
151 #include <dt-bindings/gce/mt8183-gce.h>
152 #include <dt-bindings/power/mt8183-power.h>
153 #include <dt-bindings/memory/mt8183-larb-port.h>
155 dma-controller@14001000 {
156 compatible = "mediatek,mt8183-mdp3-rdma";
158 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
159 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
161 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
167 #dma-cells = <1>;