1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ASPEED AST2700 mailbox controller 8 9maintainers: 10 - Jammy Huang <jammy_huang@aspeedtech.com> 11 12description: > 13 ASPEED AST2700 has multiple processors that need to communicate with each 14 other. The mailbox controller provides a way for these processors to send 15 messages to each other. It is a hardware-based inter-processor communication 16 mechanism that allows processors to send and receive messages through 17 dedicated channels. 18 19 The mailbox's tx/rx are independent, meaning that one processor can send a 20 message while another processor is receiving a message simultaneously. 21 There are 4 channels available for both tx and rx operations. Each channel 22 has a FIFO buffer that can hold messages of a fixed size (32 bytes in this 23 case). 24 25 The mailbox controller also supports interrupt generation, allowing 26 processors to notify each other when a message is available or when an event 27 occurs. 28 29properties: 30 compatible: 31 const: aspeed,ast2700-mailbox 32 33 reg: 34 items: 35 - description: TX control register 36 - description: RX control register 37 38 reg-names: 39 items: 40 - const: tx 41 - const: rx 42 43 interrupts: 44 maxItems: 1 45 46 "#mbox-cells": 47 const: 1 48 49required: 50 - compatible 51 - reg 52 - reg-names 53 - interrupts 54 - "#mbox-cells" 55 56additionalProperties: false 57 58examples: 59 - | 60 #include <dt-bindings/interrupt-controller/arm-gic.h> 61 62 mailbox@12c1c200 { 63 compatible = "aspeed,ast2700-mailbox"; 64 reg = <0x12c1c200 0x100>, <0x12c1c300 0x100>; 65 reg-names = "tx", "rx"; 66 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 67 #mbox-cells = <1>; 68 }; 69