Lines Matching +full:inter +full:- +full:processor

1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <asm-generic/pgtable-nopud.h>
10 #include <asm-generic/pgtable-nopmd.h>
17  * we simulate an x86-style page table for the linux mm code
23 #include <asm/processor.h>
27  * systems, only one PxTLB inter processor broadcast can be active at any one
58 	mtsp(mm->context.space_id, SR_TEMP1);  in purge_tlb_entries()
107 #define BITS_PER_PTE	(PAGE_SHIFT - BITS_PER_PTE_ENTRY)
114 #define PMD_MASK	(~(PMD_SIZE-1))
115 #define BITS_PER_PMD	(PAGE_SHIFT + PMD_TABLE_ORDER - BITS_PER_PMD_ENTRY)
123 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_TABLE_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
124 #define BITS_PER_PGD	(BITS_PER_LONG - PGDIR_SHIFT)
126 #define BITS_PER_PGD	(PAGE_SHIFT + PGD_TABLE_ORDER - BITS_PER_PGD_ENTRY)
129 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
136 #define SPACEID_SHIFT	(MAX_ADDRBITS - 32)
146 # define PT_INITIAL	(1 << (KERNEL_INITIAL_ORDER - PLD_SHIFT - BITS_PER_PTE))
156 /*     of the following bits, so be careful (One example, bits 25-31  */
180 #define xlate_pabit(x) (31 - x)
216  * are page-aligned, we don't care about the PAGE_OFFSET bits, except
217  * for a few meta-information bits, so we shift the address to be
218  * able to effectively address 40/42/44-bits of physical address space
227 #define PxD_VALUE_SHIFT   (PFN_PTE_SHIFT-PxD_FLAG_SHIFT)
235    in the short term - dhd@linuxcare.com, 2000-08-08 */
250  * We could have an execute only page using "gateway - promote to priv
261 /* initial page tables for 0-8MB for kernel */
271  * for zero-mapped memory areas etc..
375 /* Find an entry in the second-level page table.. */
387 		if (--nr == 0)  in set_ptes()
412  *   <---------------- offset -----------------> P E <ofs> < type ->
460 	set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));  in ptep_test_and_clear_young()
478 /* TLB page size encoding - see table 3-1 in parisc20.pdf */