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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts1 /dts-v1/;
2 #include <dt-bindings/gpio/gpio.h>
5 #size-cells = <0x02>;
6 #address-cells = <0x02>;
8 compatible = "microwatt-soc";
15 reserved-memory {
16 #size-cells = <0x02>;
17 #address-cells = <0x02>;
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
[all …]
/linux/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
22 unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; member
26 * Utility Routine to erase a J-TLB entry
63 /* Locate the TLB entry for this vaddr + ASID */ in tlb_entry_erase()
82 * This also sets up PD0 (vaddr, ASID..) for final commit in tlb_entry_insert()
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
95 /* setup the other half of TLB entry (pfn, rwx..) */ in tlb_entry_insert()
101 * which doesn't flush uTLBs. I'd rather be safe than sorry. in tlb_entry_insert()
[all …]
/linux/arch/powerpc/kernel/
H A Dsetup_64.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 #include <asm/asm-prototypes.h>
63 #include <asm/text-patching.h>
68 #include <asm/feature-fixups.h>
101 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
103 * set up this TLB. in setup_tlb_core_data()
108 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
112 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data()
127 /* Look for ibm,smt-enabled OF option */
151 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
[all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-44x.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Because of the 3 word TLB entries to support 36-bit addressing,
11 * are easily loaded during exception processing. I decided to
16 * ERPN fields in the TLB. -Matt
19 * easier to move into the TLB from the PTE. -BenH.
25 * PPC 440 core has following TLB attribute fields;
29 * RPN................................. - - - - - - ERPN.......
33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
43 * into TLB entry.
45 * - PRESENT *must* be in the bottom three bits because swap cache
[all …]
H A Dpte-85xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
14 - PRESENT *must* be in the bottom two bits because swap PTEs use
19 /* Definitions for FSL Book-E Cores */
30 #define _PAGE_NO_CACHE 0x00200 /* H: I bit */
44 * We define 2 sets of base prot bits, one for basic pages (ie,
56 #include <asm/pgtable-masks.h>
/linux/arch/mips/kvm/
H A Dtlb.c6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
42 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
79 * clear_root_gid() - Set GuestCtl1.RID for normal root operation.
90 * set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID.
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
[all …]
/linux/arch/parisc/include/asm/
H A Dropes.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/parisc-device.h>
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
30 void __iomem *ioc_hpa; /* I/O MMU base address */
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
38 unsigned long *res_hint; /* next avail IOVP - circular search */
85 unsigned int num_ioc; /* number of on-board IOC's */
99 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO()
103 return d->id.hversion == IKE_MERCED_PORT; in IS_IKE()
[all …]
/linux/arch/powerpc/mm/
H A Dinit_32.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
37 #include <asm/tlb.h>
47 /* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */
48 #if (CONFIG_LOWMEM_SIZE > (0xF0000000 - PAGE_OFFSET))
77 * MMU_init sets up the basic memory mappings for the kernel,
78 * including both RAM and possibly some I/O regions,
79 * and sets up the page tables and the MMU hardware ready to go.
86 total_lowmem = total_memory = memblock_end_of_DRAM() - memstart_addr; in MMU_init()
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/linux/arch/openrisc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OpenRISC tlb.c
11 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
29 #define NO_CONTEXT -1
35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
38 * Invalidate all TLB entries.
48 int i; in local_flush_tlb_all() local
51 /* Determine number of sets for IMMU. */ in local_flush_tlb_all()
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/linux/arch/powerpc/kvm/
H A De500_mmu_host.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved.
30 #include <asm/pte-walk.h>
38 #define to_htlb1_esel(esel) (host_tlb_params[1].entries - (esel) - 1)
45 return host_tlb_params[1].entries - tlbcam_index - 1; in tlb1_max_shadow_size()
70 * writing shadow tlb entry to host TLB
80 mtspr(SPRN_MAS1, stlbe->mas1); in __write_host_tlbe()
81 mtspr(SPRN_MAS2, (unsigned long)stlbe->mas2); in __write_host_tlbe()
82 mtspr(SPRN_MAS3, (u32)stlbe->mas7_3); in __write_host_tlbe()
83 mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32)); in __write_host_tlbe()
[all …]
H A De500_mmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved.
41 victim = vcpu_e500->gtlb_nv[0]++; in gtlb0_get_next_victim()
42 if (unlikely(vcpu_e500->gtlb_nv[0] >= vcpu_e500->gtlb_params[0].ways)) in gtlb0_get_next_victim()
43 vcpu_e500->gtlb_nv[0] = 0; in gtlb0_get_next_victim()
48 static int tlb0_set_base(gva_t addr, int sets, int ways) in tlb0_set_base() argument
52 set_base = (addr >> PAGE_SHIFT) & (sets - 1); in tlb0_set_base()
60 return tlb0_set_base(addr, vcpu_e500->gtlb_params[0].sets, in gtlb0_set_base()
61 vcpu_e500->gtlb_params[0].ways); in gtlb0_set_base()
70 esel &= vcpu_e500->gtlb_params[0].ways - 1; in get_tlb_esel()
[all …]
/linux/arch/powerpc/mm/book3s64/
H A Dradix_tlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TLB flush routines for radix kernels.
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
15 #include <asm/ppc-opcode.h>
16 #include <asm/tlb.h>
26 * i.e., r=1 and is=01 or is=10 or is=11
39 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs) in tlbiel_radix_set_isa300()
50 * Flush the first set of the TLB, and the entire Page Walk Cache in tlbiel_all_isa300()
51 * and partition table entries. Then flush the remaining sets of the in tlbiel_all_isa300()
52 * TLB. in tlbiel_all_isa300()
[all …]
/linux/arch/arm/mm/
H A Dproc-arm720.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
8 * hacked for non-paged-MM by Hyok S. Choi, 2004.
10 * These are the low level assembler for performing cache and TLB
15 * 05-09-2000 SJH Created by moving 720 specific functions
16 * out of 'proc-arm6,7.S' per RMK discussion
17 * 07-25-2000 SJH Added idle function.
18 * 08-25-2000 DBS Updated for integration of ARM Ltd version.
19 * 04-20-2004 HSC modified for non-paged memory management mode.
26 #include <asm/asm-offsets.h>
[all …]
/linux/arch/x86/mm/
H A Dpgtable.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <asm/tlb.h>
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
21 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) in ___pte_free_tlb() argument
24 tlb_remove_ptdesc(tlb, page_ptdesc(pte)); in ___pte_free_tlb()
28 void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) in ___pmd_free_tlb() argument
32 * NOTE! For PAE, any changes to the top page-directory-pointer-table in ___pmd_free_tlb()
36 tlb->need_flush_all = 1; in ___pmd_free_tlb()
38 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pmd)); in ___pmd_free_tlb()
42 void ___pud_free_tlb(struct mmu_gather *tlb, pud_t *pud) in ___pud_free_tlb() argument
[all …]
/linux/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include <asm/asm-const.h>
46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
128 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
129 #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
130 #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */
131 #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
192 return -1; in shift_to_mmu_psize()
211 return -1; in ap_to_shift()
249 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) argument
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/linux/Documentation/arch/x86/
H A Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
62 to perform I/O operations via use of PASID.
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
[all …]
/linux/arch/parisc/mm/
H A Dfault.c39 * parisc_acctyp(unsigned int inst) --
40 * Given a PA-RISC memory access instruction, determine if the
45 * instruction (i.e. you should really only call it if you know that
81 * older PA-RISC platforms. The case where a block in parisc_acctyp()
89 * 01 Graphics flush write (IO space -> VM) in parisc_acctyp()
90 * 10 Graphics flush read (VM -> IO space) in parisc_acctyp()
91 * 11 Graphics flush read/write (VM <-> IO space) in parisc_acctyp()
106 * Data TLB miss fault/data page fault in parisc_acctyp()
127 * not, but I want it committed to CVS so I don't lose it :-)
130 if (tree->vm_start > addr) {
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/linux/arch/mips/mm/
H A Dc-octeon.c6 * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
33 * Octeon automatically flushes the dcache on tlb changes, so
49 * Flush local I-cache for the specified range.
58 * octeon_flush_icache_all_cores - Flush caches as necessary for all cores
82 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores()
109 * octeon_flush_cache_mm - flush all memory associated with a memory context.
133 * octeon_flush_cache_range - Flush a range out of a vma
142 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range()
[all …]
/linux/arch/microblaze/include/asm/
H A Dpgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
17 #include <asm-generic/pgtable-nopmd.h>
60 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
64 * We use the hash table as an extended TLB, i.e. a cache of currently
65 * active mappings. We maintain a two-level page table tree, much
67 * management code. Low-level assembler code in hashtable.S
74 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
75 * instruction and data sides share a unified, 64-entry, semi-associative
[all …]
/linux/arch/parisc/include/uapi/asm/
H A Dpdc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
[all …]
/linux/arch/arm64/kvm/
H A Dnested.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 - Columbia University and Linaro Ltd.
28 /* -1 when not mapped on a CPU */
32 * true if the TLB is valid. Can only be changed with the
39 * Ratio of live shadow S2 MMU per vcpu. This is a trade-off between
40 * memory usage and potential number of different sets of S2 PTs in
48 kvm->arch.nested_mmus = NULL; in kvm_init_nested()
49 kvm->arch.nested_mmus_size = 0; in kvm_init_nested()
50 atomic_set(&kvm->arch.vncr_map_count, 0); in kvm_init_nested()
70 struct kvm *kvm = vcpu->kvm; in kvm_vcpu_init_nested()
[all …]
/linux/kernel/dma/
H A Dswiotlb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * I/O TLBs (aka DMA address translation hardware).
9 * Copyright (C) 2000, 2003 Hewlett-Packard Co
10 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
14 * unnecessary i-cach
273 unsigned long bytes = nslabs << IO_TLB_SHIFT, i; swiotlb_init_io_tlb_pool() local
320 swiotlb_memblock_alloc(unsigned long nslabs,unsigned int flags,int (* remap)(void * tlb,unsigned long nslabs)) swiotlb_memblock_alloc() argument
323 void *tlb; swiotlb_memblock_alloc() local
355 swiotlb_init_remap(bool addressing_limit,unsigned int flags,int (* remap)(void * tlb,unsigned long nslabs)) swiotlb_init_remap() argument
361 void *tlb; swiotlb_init_remap() local
431 swiotlb_init_late(size_t size,gfp_t gfp_mask,int (* remap)(void * tlb,unsigned long nslabs)) swiotlb_init_late() argument
689 struct page *tlb; swiotlb_alloc_pool() local
1028 unsigned int index, slots_checked, count = 0, i; swiotlb_search_pool_area() local
1190 int cpu, i; swiotlb_find_slots() local
1262 int start, i; swiotlb_find_slots() local
1308 int i; mem_pool_used() local
1376 unsigned int i; swiotlb_tbl_map_single() local
1450 int count, i; swiotlb_release_slots() local
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