6  * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
33  * Octeon automatically flushes the dcache on tlb changes, so
49  * Flush local I-cache for the specified range.
58  * octeon_flush_icache_all_cores -  Flush caches as necessary for all cores
82 		mask = *mm_cpumask(vma->vm_mm);  in octeon_flush_icache_all_cores()
109  * octeon_flush_cache_mm - flush all memory associated with a memory context.
133  * octeon_flush_cache_range - Flush a range out of a vma
142 	if (vma->vm_flags & VM_EXEC)  in octeon_flush_cache_range()
148  * octeon_flush_cache_page - Flush a specific page of a vma
157 	if (vma->vm_flags & VM_EXEC)  in octeon_flush_cache_page()
182 		c->icache.linesz = 2 << ((config1 >> 19) & 7);  in probe_octeon()
183 		c->icache.sets = 64 << ((config1 >> 22) & 7);  in probe_octeon()
184 		c->icache.ways = 1 + ((config1 >> 16) & 7);  in probe_octeon()
185 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
187 			c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
188 		c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;  in probe_octeon()
189 		c->dcache.linesz = 128;  in probe_octeon()
191 			c->dcache.sets = 2; /* CN5XXX has two Dcache sets */  in probe_octeon()
193 			c->dcache.sets = 1; /* CN3XXX has one Dcache set */  in probe_octeon()
194 		c->dcache.ways = 64;  in probe_octeon()
196 			c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
197 		c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;  in probe_octeon()
198 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
202 		c->icache.linesz = 2 << ((config1 >> 19) & 7);  in probe_octeon()
203 		c->icache.sets = 8;  in probe_octeon()
204 		c->icache.ways = 37;  in probe_octeon()
205 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
206 		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
208 		c->dcache.linesz = 128;  in probe_octeon()
209 		c->dcache.ways = 32;  in probe_octeon()
210 		c->dcache.sets = 8;  in probe_octeon()
211 		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
212 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
216 		c->icache.linesz = 128;  in probe_octeon()
217 		c->icache.sets = 16;  in probe_octeon()
218 		c->icache.ways = 39;  in probe_octeon()
219 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
220 		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
222 		c->dcache.linesz = 128;  in probe_octeon()
223 		c->dcache.ways = 32;  in probe_octeon()
224 		c->dcache.sets = 8;  in probe_octeon()
225 		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
226 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
235 	c->icache.waysize = icache_size / c->icache.ways;  in probe_octeon()
236 	c->dcache.waysize = dcache_size / c->dcache.ways;  in probe_octeon()
238 	c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);  in probe_octeon()
239 	c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);  in probe_octeon()
243 			"%d sets, linesize %d bytes.\n",  in probe_octeon()
247 			c->icache.ways, c->icache.sets, c->icache.linesz);  in probe_octeon()
249 		pr_info("Primary data cache %ldkB, %d-way, %d sets, "  in probe_octeon()
251 			dcache_size >> 10, c->dcache.ways,  in probe_octeon()
252 			c->dcache.sets, c->dcache.linesz);  in probe_octeon()
270 	shm_align_mask = PAGE_SIZE - 1;  in octeon_cache_init()