Lines Matching +full:i +full:- +full:tlb +full:- +full:sets
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
28 - $ref: extensions.yaml
33 - items:
34 - enum:
35 - amd,mbv32
36 - andestech,ax45mp
37 - canaan,k210
38 - sifive,bullet0
39 - sifive,e5
40 - sifive,e7
41 - sifive,e71
42 - sifive,rocket0
43 - sifive,s7
44 - sifive,u5
45 - sifive,u54
46 - sifive,u7
47 - sifive,u74
48 - sifive,u74-mc
49 - thead,c906
50 - thead,c908
51 - thead,c910
52 - thead,c920
53 - const: riscv
54 - items:
55 - enum:
56 - sifive,e51
57 - sifive,u54-mc
58 - const: sifive,rocket0
59 - const: riscv
60 - const: riscv # Simulator only
62 Identifies that the hart uses the RISC-V instruction set
65 mmu-type:
68 this hart. These values originate from the RISC-V Privileged
73 - riscv,sv32
74 - riscv,sv39
75 - riscv,sv48
76 - riscv,sv57
77 - riscv,none
83 riscv,cbom-block-size:
88 riscv,cbop-block-size:
93 riscv,cboz-block-size:
98 # RISC-V has multiple properties for cache op block sizes as the sizes
100 cache-op-block-size: false
101 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
102 timebase-frequency: false
104 interrupt-controller:
106 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
108 cpu-idle-states:
109 $ref: /schemas/types.yaml#/definitions/phandle-array
114 by this hart (see ./idle-states.yaml).
116 capacity-dmips-mhz:
118 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
119 DMIPS/MHz, relative to highest capacity-dmips-mhz
123 - required:
124 - riscv,isa
125 - required:
126 - riscv,isa-base
129 riscv,isa-base: [ "riscv,isa-extensions" ]
130 riscv,isa-extensions: [ "riscv,isa-base" ]
133 - interrupt-controller
138 - |
141 #address-cells = <1>;
142 #size-cells = <0>;
143 timebase-frequency = <1000000>;
145 clock-frequency = <0>;
148 i-cache-block-size = <64>;
149 i-cache-sets = <128>;
150 i-cache-size = <16384>;
152 riscv,isa-base = "rv64i";
153 riscv,isa-extensions = "i", "m", "a", "c";
155 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1>;
157 compatible = "riscv,cpu-intc";
158 interrupt-controller;
162 clock-frequency = <0>;
164 d-cache-block-size = <64>;
165 d-cache-sets = <64>;
166 d-cache-size = <32768>;
167 d-tlb-sets = <1>;
168 d-tlb-size = <32>;
170 i-cache-block-size = <64>;
171 i-cache-sets = <64>;
172 i-cache-size = <32768>;
173 i-tlb-sets = <1>;
174 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39";
177 tlb-split;
178 riscv,isa-base = "rv64i";
179 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
181 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1>;
183 compatible = "riscv,cpu-intc";
184 interrupt-controller;
189 - |
192 #address-cells = <1>;
193 #size-cells = <0>;
198 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i";
200 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
202 interrupt-controller {
203 #interrupt-cells = <1>;
204 interrupt-controller;
205 compatible = "riscv,cpu-intc";