/linux/arch/riscv/boot/dts/sophgo/ |
H A D | sg2042-cpus.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 #address-cells = <1>; 9 #size-cells = <0>; 10 timebase-frequency = <50000000>; 12 cpu-map { 260 riscv,isa-base = "rv64i"; 261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 265 i-cache-block-size = <64>; 266 i-cache-size = <65536>; 267 i-cache-sets = <512>; [all …]
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/linux/arch/arm64/boot/dts/amazon/ |
H A D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 compatible = "amazon,al-alpine-v3"; 14 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 #address-cells = <1>; 21 #size-cells = <0>; 25 compatible = "arm,cortex-a72"; [all …]
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/linux/arch/arm64/boot/dts/amd/ |
H A D | amd-seattle-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 #address-cells = <0x1>; 6 #size-cells = <0x0>; 8 cpu-map { 45 compatible = "arm,cortex-a57"; 47 enable-method = "psci"; 49 i-cache-size = <0xC000>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <256>; 52 d-cache-size = <0x8000>; [all …]
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/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-j784s4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 11 #include "k3-j784s4-j742s2-common.dtsi" 18 #address-cells = <1>; 19 #size-cells = <0>; 20 cpu-map { 59 compatible = "arm,cortex-a72"; 62 enable-method = "psci"; 63 i-cache-size = <0xc000>; 64 i-cache-line-size = <64>; [all …]
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H A D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include "k3-am65.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 14 cpu-map { 37 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; 41 i-cache-size = <0x8000>; 42 i-cache-line-size = <64>; [all …]
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H A D | k3-am625.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 10 /dts-v1/; 12 #include "k3-am62.dtsi" 16 #address-cells = <1>; 17 #size-cells = <0>; 19 cpu-map { 40 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 i-cache-size = <0x8000>; [all …]
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H A D | k3-am642.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 /dts-v1/; 10 #include "k3-am64.dtsi" 14 #address-cells = <1>; 15 #size-cells = <0>; 17 cpu-map { 30 compatible = "arm,cortex-a53"; 33 enable-method = "psci"; 34 i-cache-size = <0x8000>; [all …]
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H A D | k3-am652.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include "k3-am65.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 14 cpu-map { 27 compatible = "arm,cortex-a53"; 30 enable-method = "psci"; 31 i-cache-size = <0x8000>; 32 i-cache-line-size = <64>; [all …]
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H A D | k3-j722s.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 13 #include "k3-pinctrl.h" 18 interrupt-parent = <&gic500>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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/linux/arch/arm64/boot/dts/marvell/ |
H A D | armada-ap806-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap806.dtsi" 12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; 15 #address-cells = <1>; 16 #size-cells = <0>; 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; [all …]
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H A D | armada-ap807-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap807.dtsi" 12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; 15 #address-cells = <1>; 16 #size-cells = <0>; 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; [all …]
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H A D | armada-ap806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap806.dtsi" 12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; 15 #address-cells = <1>; 16 #size-cells = <0>; 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; [all …]
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/linux/arch/arm64/boot/dts/arm/ |
H A D | fvp-base-revc.dts | 1 // SPDX-License-Identifier: GPL-2.0 5 * Architecture Envelope Model (AEM) ARMv8-A 11 /dts-v1/; 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 17 #include "rtsm_ve-motherboard.dtsi" 18 #include "rtsm_ve-motherboard-rs2.dtsi" 22 compatible = "arm,fvp-base-revc", "arm,vexpress"; 23 interrupt-parent = <&gic>; 24 #address-cells = <2>; 25 #size-cells = <2>; [all …]
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H A D | juno-r2.dts | 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 14 #include "juno-cs-r1r2.dtsi" 18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 28 stdout-path = "serial0:115200n8"; [all …]
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H A D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd. 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 27 stdout-path = "serial0:115200n8"; 31 compatible = "arm,psci-0.2"; [all …]
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H A D | juno-r1.dts | 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 14 #include "juno-cs-r1r2.dtsi" 18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 28 stdout-path = "serial0:115200n8"; [all …]
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/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi" 10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 12 local_intc: interrupt-controller@40000000 { 13 compatible = "brcm,bcm2836-l1-intc"; 15 interrupt-controller; 16 #interrupt-cells = <2>; 17 interrupt-parent = <&local_intc>; 21 arm-pmu { 22 compatible = "arm,cortex-a53-pmu"; 23 interrupt-parent = <&local_intc>; [all …]
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H A D | bcm2836.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include "bcm2835-common.dtsi" 11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 13 local_intc: interrupt-controller@40000000 { 14 compatible = "brcm,bcm2836-l1-intc"; 16 interrupt-controller; 17 #interrupt-cells = <2>; 18 interrupt-parent = <&local_intc>; 22 arm-pmu { 23 compatible = "arm,cortex-a7-pmu"; [all …]
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/linux/arch/riscv/boot/dts/sifive/ |
H A D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2018-2019 SiFive, Inc */ 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu540-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu540-c000", "sifive,fu540"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; [all …]
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H A D | fu740-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu740-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu740-c000", "sifive,fu740"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; 29 i-cache-sets = <128>; [all …]
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/linux/arch/arm64/boot/dts/broadcom/ |
H A D | bcm2712.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #address-cells = <2>; 8 #size-cells = <2>; 10 interrupt-parent = <&gicv2>; 14 clk_osc: clk-osc { 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-output-names = "osc"; 18 clock-frequency = <54000000>; [all …]
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/linux/arch/riscv/boot/dts/microchip/ |
H A D | mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <1000000>; 21 i-cache-block-size = <64>; [all …]
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/linux/arch/arm64/boot/dts/tesla/ |
H A D | fsd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Tesla Full Self-Driving SoC device tree source 5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2017-2022 Tesla, Inc. 11 #include <dt-bindings/clock/fsd-clk.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 38 #address-cells = <2>; [all …]
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/linux/arch/arm64/boot/dts/freescale/ |
H A D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 // Device Tree Include file for Layerscape-LX2160A family SoC. 5 // Copyright 2018-2020 NXP 7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; [all …]
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H A D | imx8qm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/pinctrl/pads-imx8qm.h> 12 #include <dt-bindings/thermal/thermal.h> 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; [all …]
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