1*89bd4c37SNishanth Menon// SPDX-License-Identifier: GPL-2.0-only OR MIT 25fc6b1b6SVignesh Raghavendra/* 35fc6b1b6SVignesh Raghavendra * Device Tree Source for AM62A7 SoC family in Quad core configuration 45fc6b1b6SVignesh Raghavendra * 55fc6b1b6SVignesh Raghavendra * TRM: https://www.ti.com/lit/zip/spruj16 65fc6b1b6SVignesh Raghavendra * 7*89bd4c37SNishanth Menon * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 85fc6b1b6SVignesh Raghavendra */ 95fc6b1b6SVignesh Raghavendra 105fc6b1b6SVignesh Raghavendra/dts-v1/; 115fc6b1b6SVignesh Raghavendra 125fc6b1b6SVignesh Raghavendra#include "k3-am62a.dtsi" 135fc6b1b6SVignesh Raghavendra 145fc6b1b6SVignesh Raghavendra/ { 155fc6b1b6SVignesh Raghavendra cpus { 165fc6b1b6SVignesh Raghavendra #address-cells = <1>; 175fc6b1b6SVignesh Raghavendra #size-cells = <0>; 185fc6b1b6SVignesh Raghavendra 195fc6b1b6SVignesh Raghavendra cpu-map { 205fc6b1b6SVignesh Raghavendra cluster0: cluster0 { 215fc6b1b6SVignesh Raghavendra core0 { 225fc6b1b6SVignesh Raghavendra cpu = <&cpu0>; 235fc6b1b6SVignesh Raghavendra }; 245fc6b1b6SVignesh Raghavendra 255fc6b1b6SVignesh Raghavendra core1 { 265fc6b1b6SVignesh Raghavendra cpu = <&cpu1>; 275fc6b1b6SVignesh Raghavendra }; 285fc6b1b6SVignesh Raghavendra 295fc6b1b6SVignesh Raghavendra core2 { 305fc6b1b6SVignesh Raghavendra cpu = <&cpu2>; 315fc6b1b6SVignesh Raghavendra }; 325fc6b1b6SVignesh Raghavendra 335fc6b1b6SVignesh Raghavendra core3 { 345fc6b1b6SVignesh Raghavendra cpu = <&cpu3>; 355fc6b1b6SVignesh Raghavendra }; 365fc6b1b6SVignesh Raghavendra }; 375fc6b1b6SVignesh Raghavendra }; 385fc6b1b6SVignesh Raghavendra 395fc6b1b6SVignesh Raghavendra cpu0: cpu@0 { 405fc6b1b6SVignesh Raghavendra compatible = "arm,cortex-a53"; 415fc6b1b6SVignesh Raghavendra reg = <0x000>; 425fc6b1b6SVignesh Raghavendra device_type = "cpu"; 435fc6b1b6SVignesh Raghavendra enable-method = "psci"; 445fc6b1b6SVignesh Raghavendra i-cache-size = <0x8000>; 455fc6b1b6SVignesh Raghavendra i-cache-line-size = <64>; 465fc6b1b6SVignesh Raghavendra i-cache-sets = <256>; 475fc6b1b6SVignesh Raghavendra d-cache-size = <0x8000>; 485fc6b1b6SVignesh Raghavendra d-cache-line-size = <64>; 495fc6b1b6SVignesh Raghavendra d-cache-sets = <128>; 505fc6b1b6SVignesh Raghavendra next-level-cache = <&L2_0>; 515fc6b1b6SVignesh Raghavendra }; 525fc6b1b6SVignesh Raghavendra 535fc6b1b6SVignesh Raghavendra cpu1: cpu@1 { 545fc6b1b6SVignesh Raghavendra compatible = "arm,cortex-a53"; 555fc6b1b6SVignesh Raghavendra reg = <0x001>; 565fc6b1b6SVignesh Raghavendra device_type = "cpu"; 575fc6b1b6SVignesh Raghavendra enable-method = "psci"; 585fc6b1b6SVignesh Raghavendra i-cache-size = <0x8000>; 595fc6b1b6SVignesh Raghavendra i-cache-line-size = <64>; 605fc6b1b6SVignesh Raghavendra i-cache-sets = <256>; 615fc6b1b6SVignesh Raghavendra d-cache-size = <0x8000>; 625fc6b1b6SVignesh Raghavendra d-cache-line-size = <64>; 635fc6b1b6SVignesh Raghavendra d-cache-sets = <128>; 645fc6b1b6SVignesh Raghavendra next-level-cache = <&L2_0>; 655fc6b1b6SVignesh Raghavendra }; 665fc6b1b6SVignesh Raghavendra 675fc6b1b6SVignesh Raghavendra cpu2: cpu@2 { 685fc6b1b6SVignesh Raghavendra compatible = "arm,cortex-a53"; 695fc6b1b6SVignesh Raghavendra reg = <0x002>; 705fc6b1b6SVignesh Raghavendra device_type = "cpu"; 715fc6b1b6SVignesh Raghavendra enable-method = "psci"; 725fc6b1b6SVignesh Raghavendra i-cache-size = <0x8000>; 735fc6b1b6SVignesh Raghavendra i-cache-line-size = <64>; 745fc6b1b6SVignesh Raghavendra i-cache-sets = <256>; 755fc6b1b6SVignesh Raghavendra d-cache-size = <0x8000>; 765fc6b1b6SVignesh Raghavendra d-cache-line-size = <64>; 775fc6b1b6SVignesh Raghavendra d-cache-sets = <128>; 785fc6b1b6SVignesh Raghavendra next-level-cache = <&L2_0>; 795fc6b1b6SVignesh Raghavendra }; 805fc6b1b6SVignesh Raghavendra 815fc6b1b6SVignesh Raghavendra cpu3: cpu@3 { 825fc6b1b6SVignesh Raghavendra compatible = "arm,cortex-a53"; 835fc6b1b6SVignesh Raghavendra reg = <0x003>; 845fc6b1b6SVignesh Raghavendra device_type = "cpu"; 855fc6b1b6SVignesh Raghavendra enable-method = "psci"; 865fc6b1b6SVignesh Raghavendra i-cache-size = <0x8000>; 875fc6b1b6SVignesh Raghavendra i-cache-line-size = <64>; 885fc6b1b6SVignesh Raghavendra i-cache-sets = <256>; 895fc6b1b6SVignesh Raghavendra d-cache-size = <0x8000>; 905fc6b1b6SVignesh Raghavendra d-cache-line-size = <64>; 915fc6b1b6SVignesh Raghavendra d-cache-sets = <128>; 925fc6b1b6SVignesh Raghavendra next-level-cache = <&L2_0>; 935fc6b1b6SVignesh Raghavendra }; 945fc6b1b6SVignesh Raghavendra }; 955fc6b1b6SVignesh Raghavendra 965fc6b1b6SVignesh Raghavendra L2_0: l2-cache0 { 975fc6b1b6SVignesh Raghavendra compatible = "cache"; 98880932e6SPierre Gondois cache-unified; 995fc6b1b6SVignesh Raghavendra cache-level = <2>; 100438b8dc9SVignesh Raghavendra cache-size = <0x80000>; 1015fc6b1b6SVignesh Raghavendra cache-line-size = <64>; 1025fc6b1b6SVignesh Raghavendra cache-sets = <512>; 1035fc6b1b6SVignesh Raghavendra }; 1045fc6b1b6SVignesh Raghavendra}; 105