1*5f016758SVignesh Raghavendra// SPDX-License-Identifier: GPL-2.0-only or MIT 2*5f016758SVignesh Raghavendra/* 3*5f016758SVignesh Raghavendra * Device Tree file for the AM62L3 SoC family (Dual Core A53) 4*5f016758SVignesh Raghavendra * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ 5*5f016758SVignesh Raghavendra * 6*5f016758SVignesh Raghavendra * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 7*5f016758SVignesh Raghavendra */ 8*5f016758SVignesh Raghavendra 9*5f016758SVignesh Raghavendra/dts-v1/; 10*5f016758SVignesh Raghavendra 11*5f016758SVignesh Raghavendra#include "k3-am62l.dtsi" 12*5f016758SVignesh Raghavendra 13*5f016758SVignesh Raghavendra/ { 14*5f016758SVignesh Raghavendra cpus { 15*5f016758SVignesh Raghavendra #address-cells = <1>; 16*5f016758SVignesh Raghavendra #size-cells = <0>; 17*5f016758SVignesh Raghavendra 18*5f016758SVignesh Raghavendra cpu-map { 19*5f016758SVignesh Raghavendra cluster0: cluster0 { 20*5f016758SVignesh Raghavendra core0 { 21*5f016758SVignesh Raghavendra cpu = <&cpu0>; 22*5f016758SVignesh Raghavendra }; 23*5f016758SVignesh Raghavendra 24*5f016758SVignesh Raghavendra core1 { 25*5f016758SVignesh Raghavendra cpu = <&cpu1>; 26*5f016758SVignesh Raghavendra }; 27*5f016758SVignesh Raghavendra }; 28*5f016758SVignesh Raghavendra }; 29*5f016758SVignesh Raghavendra 30*5f016758SVignesh Raghavendra cpu0: cpu@0 { 31*5f016758SVignesh Raghavendra compatible = "arm,cortex-a53"; 32*5f016758SVignesh Raghavendra reg = <0x000>; 33*5f016758SVignesh Raghavendra device_type = "cpu"; 34*5f016758SVignesh Raghavendra enable-method = "psci"; 35*5f016758SVignesh Raghavendra i-cache-size = <0x8000>; 36*5f016758SVignesh Raghavendra i-cache-line-size = <64>; 37*5f016758SVignesh Raghavendra i-cache-sets = <256>; 38*5f016758SVignesh Raghavendra d-cache-size = <0x8000>; 39*5f016758SVignesh Raghavendra d-cache-line-size = <64>; 40*5f016758SVignesh Raghavendra d-cache-sets = <128>; 41*5f016758SVignesh Raghavendra next-level-cache = <&l2_0>; 42*5f016758SVignesh Raghavendra }; 43*5f016758SVignesh Raghavendra 44*5f016758SVignesh Raghavendra cpu1: cpu@1 { 45*5f016758SVignesh Raghavendra compatible = "arm,cortex-a53"; 46*5f016758SVignesh Raghavendra reg = <0x001>; 47*5f016758SVignesh Raghavendra device_type = "cpu"; 48*5f016758SVignesh Raghavendra enable-method = "psci"; 49*5f016758SVignesh Raghavendra i-cache-size = <0x8000>; 50*5f016758SVignesh Raghavendra i-cache-line-size = <64>; 51*5f016758SVignesh Raghavendra i-cache-sets = <256>; 52*5f016758SVignesh Raghavendra d-cache-size = <0x8000>; 53*5f016758SVignesh Raghavendra d-cache-line-size = <64>; 54*5f016758SVignesh Raghavendra d-cache-sets = <128>; 55*5f016758SVignesh Raghavendra next-level-cache = <&l2_0>; 56*5f016758SVignesh Raghavendra }; 57*5f016758SVignesh Raghavendra }; 58*5f016758SVignesh Raghavendra 59*5f016758SVignesh Raghavendra l2_0: l2-cache0 { 60*5f016758SVignesh Raghavendra compatible = "cache"; 61*5f016758SVignesh Raghavendra cache-unified; 62*5f016758SVignesh Raghavendra cache-level = <2>; 63*5f016758SVignesh Raghavendra cache-size = <0x40000>; 64*5f016758SVignesh Raghavendra cache-line-size = <64>; 65*5f016758SVignesh Raghavendra cache-sets = <256>; 66*5f016758SVignesh Raghavendra }; 67*5f016758SVignesh Raghavendra}; 68