Lines Matching +full:i +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include "k3-j784s4-j742s2-common.dtsi"
18 #address-cells = <1>;
19 #size-cells = <0>;
20 cpu-map {
59 compatible = "arm,cortex-a72";
62 enable-method = "psci";
63 i-cache-size = <0xc000>;
64 i-cache-line-size = <64>;
65 i-cache-sets = <256>;
66 d-cache-size = <0x8000>;
67 d-cache-line-size = <64>;
68 d-cache-sets = <256>;
69 next-level-cache = <&L2_0>;
73 compatible = "arm,cortex-a72";
76 enable-method = "psci";
77 i-cache-size = <0xc000>;
78 i-cache-line-size = <64>;
79 i-cache-sets = <256>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
82 d-cache-sets = <256>;
83 next-level-cache = <&L2_0>;
87 compatible = "arm,cortex-a72";
90 enable-method = "psci";
91 i-cache-size = <0xc000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <256>;
97 next-level-cache = <&L2_0>;
101 compatible = "arm,cortex-a72";
104 enable-method = "psci";
105 i-cache-size = <0xc000>;
106 i-cache-line-size = <64>;
107 i-cache-sets = <256>;
108 d-cache-size = <0x8000>;
109 d-cache-line-size = <64>;
110 d-cache-sets = <256>;
111 next-level-cache = <&L2_0>;
115 compatible = "arm,cortex-a72";
118 enable-method = "psci";
119 i-cache-size = <0xc000>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <256>;
122 d-cache-size = <0x8000>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <256>;
125 next-level-cache = <&L2_1>;
129 compatible = "arm,cortex-a72";
132 enable-method = "psci";
133 i-cache-size = <0xc000>;
134 i-cache-line-size = <64>;
135 i-cache-sets = <256>;
136 d-cache-size = <0x8000>;
137 d-cache-line-size = <64>;
138 d-cache-sets = <256>;
139 next-level-cache = <&L2_1>;
143 compatible = "arm,cortex-a72";
146 enable-method = "psci";
147 i-cache-size = <0xc000>;
148 i-cache-line-size = <64>;
149 i-cache-sets = <256>;
150 d-cache-size = <0x8000>;
151 d-cache-line-size = <64>;
152 d-cache-sets = <256>;
153 next-level-cache = <&L2_1>;
157 compatible = "arm,cortex-a72";
160 enable-method = "psci";
161 i-cache-size = <0xc000>;
162 i-cache-line-size = <64>;
163 i-cache-sets = <256>;
164 d-cache-size = <0x8000>;
165 d-cache-line-size = <64>;
166 d-cache-sets = <256>;
167 next-level-cache = <&L2_1>;
172 #include "k3-j784s4-main.dtsi"