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/freebsd/lib/libpmc/pmu-events/arch/x86/knightslanding/
H A D	cache.json	79 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", 126 …prefetch code read requests that accounts for reponses from snoop request hit with data forwarded… 137 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 148 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 159 …prefetch code read requests that accounts for reponses from snoop request hit with data forwarded… 170 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 181 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… 192 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… 203 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… 214 …e reads and prefetch code read requests that accounts for responses which hit its own tile's L2 w… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A D	cache.json	68 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 85 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 92 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 109 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 116 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 133 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 140 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 238 "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", 246 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF… 264 …"Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A D	cache.json	63 "BriefDescription": "Not rejected writebacks that hit L2 cache", 68 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 216 "BriefDescription": "Demand Data Read requests that hit L2 cache", 222 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 238 "BriefDescription": "L2 prefetch requests that hit L2 cache", 243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 280 "BriefDescription": "RFO requests that hit L2 cache", 285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 434 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed … [all …]
H A D	virtual-memory.json	23 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 38 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 48 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 122 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … 127 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… 132 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 137 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 142 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A D	cache.json	63 "BriefDescription": "Not rejected writebacks that hit L2 cache", 68 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 216 "BriefDescription": "Demand Data Read requests that hit L2 cache", 222 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 238 "BriefDescription": "L2 prefetch requests that hit L2 cache", 243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 280 "BriefDescription": "RFO requests that hit L2 cache", 285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 434 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed … [all …]
H A D	virtual-memory.json	23 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 38 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 48 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 122 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … 127 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… 132 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 137 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 142 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	cache.json	271 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 280 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 298 "BriefDescription": "RFO requests that hit L2 cache.", 325 "BriefDescription": "RFOs that hit cache lines in E state.", 334 "BriefDescription": "RFOs that hit cache lines in M state.", 457 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 468 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 473 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 504 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 540 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	cache.json	41 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 136 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 142 …cheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable.", 148 …cheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line… 154 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 166 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 172 …eable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line… 196 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … 208 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", 214 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", [all …]
H A D	branch.json	`27 "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.", 33 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit … 39 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit … 45 …fDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit …`
/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A D	cache.json	59 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 144 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 210 "BriefDescription": "Demand Data Read requests that hit L2 cache", 216 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 234 "BriefDescription": "RFO requests that hit L2 cache", 240 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 258 "BriefDescription": "SW prefetch requests that hit L2 cache.", 264 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 440 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 448 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/ampere/emag/
H A D	cache.json	132 "PublicDescription": "Page walk cache level-0 stage-1 hit", 135 "BriefDescription": "Page walk, L0 stage-1 hit" 138 "PublicDescription": "Page walk cache level-1 stage-1 hit", 141 "BriefDescription": "Page walk, L1 stage-1 hit" 144 "PublicDescription": "Page walk cache level-2 stage-1 hit", 147 "BriefDescription": "Page walk, L2 stage-1 hit" 150 "PublicDescription": "Page walk cache level-1 stage-2 hit", 153 "BriefDescription": "Page walk, L1 stage-2 hit" 156 "PublicDescription": "Page walk cache level-2 stage-2 hit", 159 "BriefDescription": "Page walk, L2 stage-2 hit"
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A D	cache.json	39 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 46 …to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (no… 51 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 58 …e to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", 63 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… 70 …to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level C… 75 …s the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (No… 86 … "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 93 …": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", 98 …Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other… [all …]
/freebsd/lib/libpmc/
H A D	pmc.haswellxeon.3	144 -For LLC Hit, ReslHitl was returned by all cores 151 -Snoop Hit w/ Invalidation (LLC Hit, RFO) 152 -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 153 -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 158 -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 164 -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 165 -Snoop MtoS (LLC Hit, IFetch/Data_RD). 240 Load misses that missed DTLB but hit STLB (4K). 243 Load misses that missed DTLB but hit STLB (2M). 282 Demand Data Read requests that hit L2 cache. [all …]
H A D	pmc.haswell.3	143 -For LLC Hit, ReslHitl was returned by all cores 150 -Snoop Hit w/ Invalidation (LLC Hit, RFO) 151 -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 152 -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 157 -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 163 -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 164 -Snoop MtoS (LLC Hit, IFetch/Data_RD). 239 Load misses that missed DTLB but hit STLB (4K). 242 Load misses that missed DTLB but hit STLB (2M). 281 Demand Data Read requests that hit L2 cache. [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/
H A D	cache.json	28 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 55 "BriefDescription": "Not rejected writebacks that hit L2 cache", 60 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 129 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 190 "BriefDescription": "Demand Data Read requests that hit L2 cache", 195 …ounts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", 210 "BriefDescription": "L2 prefetch requests that hit L2 cache", 215 … event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefet… 248 "BriefDescription": "RFO requests that hit L2 cache.", 384 …is event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	cache.json	48 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 52 "EventName": "L2_REQUEST.HIT", 55 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 108 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRA… 118 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No… 125 …to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (no… 130 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 137 …e to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", 142 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other… 149 …to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level C… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A D	cache.json	81 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 99 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 107 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 125 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 133 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 151 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 159 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 281 "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.", 291 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE… 296 …on": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other proces… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A D	cache.json	230 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 245 "BriefDescription": "Demand Data Read requests that hit L2 cache", 250 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 255 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 260 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 275 "BriefDescription": "RFO requests that hit L2 cache", 280 "PublicDescription": "RFO requests that hit L2 cache.", 305 "BriefDescription": "RFOs that hit cache lines in M state", 310 "PublicDescription": "RFOs that hit cache lines in M state.", 455 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… [all …]
/freebsd/usr.bin/mkuzip/
H A D	mkuz_blockcache.c	43 struct mkuz_blk_info hit; member 63 if (lseek(fd, bcep->hit.offset, SEEK_SET) < 0) { in verify_match() 106 if (blkcache.first[h].hit.len == 0) { in mkuz_blkcache_regblock() 110 if (bcep->hit.len != bp->info.len) in mkuz_blkcache_regblock() 112 if (memcmp(bp->info.digest, bcep->hit.digest, in mkuz_blkcache_regblock() 121 fprintf(stderr, "cache hit %jd, %jd, %jd, %jd\n", in mkuz_blkcache_regblock() 122 I2J(bcep->hit.blkno), I2J(bcep->hit.offset), in mkuz_blkcache_regblock() 125 return (&bcep->hit); in mkuz_blkcache_regblock() 144 bcep->hit = bp->info; in mkuz_blkcache_regblock()
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A D	cache.json	271 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 280 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 298 "BriefDescription": "RFO requests that hit L2 cache.", 325 "BriefDescription": "RFOs that hit cache lines in E state.", 334 "BriefDescription": "RFOs that hit cache lines in M state.", 456 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 466 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 471 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 507 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 542 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A D	cache.json	28 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 118 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 183 "BriefDescription": "Demand Data Read requests that hit L2 cache", 188 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 213 …": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", 218 …ts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", 243 "BriefDescription": "RFO requests that hit L2 cache", 248 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 416 …"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop… 497 …on": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A D	cache.json	25 …"BriefDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 … 35 …"BriefDescription": "The number of pipeline restarts caused by invalidating probes that hit on the… 111 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 206 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 212 …ore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2.", 218 …cheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L… 224 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 236 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 242 …heable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.", 266 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … [all …]
/freebsd/sys/contrib/openzfs/man/man1/
H A D	arcstat.1	`38 Demand hit percentage 40 Demand I/O hit percentage 44 Demand data hit percentage 46 Demand data I/O hit percentage 50 Demand metadata hit percentage 52 Demand metadata I/O hit percentage 58 Metadata hit percentage 60 Metadata I/O hit percentage 101 .It Sy hit% 102 ARC hit percentage [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	65 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 153 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 213 "BriefDescription": "Demand Data Read requests that hit L2 cache", 219 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 257 "BriefDescription": "RFO requests that hit L2 cache", 263 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 279 "BriefDescription": "SW prefetch requests that hit L2 cache.", 285 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET… 443 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 451 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	cache.json	41 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis… 136 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", 142 …ore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2.", 148 …cheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L… 154 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", 166 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in … 172 …heable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.", 196 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in … 208 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", 214 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", [all …]

12 3 4 5 6 7 8 9 10 >>...49