Lines Matching full:hit
39 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (No…
46 …to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (no…
51 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
58 …e to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.",
63 …f cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other…
70 …to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level C…
75 …s the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (No…
86 … "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
93 …": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.",
98 …Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other…
105 … "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level C…
121 "BriefDescription": "Counts the number of load ops retired that hit in DRAM.",
131 "BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.",
155 "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
179 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",