Lines Matching full:hit
25 …"BriefDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 …
35 …"BriefDescription": "The number of pipeline restarts caused by invalidating probes that hit on the…
111 …n). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/mis…
206 … L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2",
212 …ore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2.",
218 …cheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L…
224 …le request access status (not including L2 Prefetch). Data cache store or state change hit in L2.",
236 …eable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in …
242 …heable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.",
266 …us (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in …
278 "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.",
284 … L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.",