xref: /freebsd/lib/libpmc/pmu-events/arch/arm64/ampere/emag/cache.json (revision 9d97138e2d138bcd03dc28f45e78b13c536bed84) 
1[
2    {
3        "ArchStdEvent": "L1D_CACHE_RD"
4    },
5    {
6        "ArchStdEvent": "L1D_CACHE_WR"
7    },
8    {
9        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
10    },
11    {
12        "ArchStdEvent": "L1D_CACHE_INVAL"
13    },
14    {
15        "ArchStdEvent": "L1D_TLB_REFILL_RD"
16    },
17    {
18        "ArchStdEvent": "L1D_TLB_REFILL_WR"
19    },
20    {
21        "ArchStdEvent": "L2D_CACHE_RD"
22    },
23    {
24        "ArchStdEvent": "L2D_CACHE_WR"
25    },
26    {
27        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
28    },
29    {
30        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
31    },
32    {
33        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
34    },
35    {
36        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
37    },
38    {
39        "ArchStdEvent": "L2D_CACHE_INVAL"
40    },
41    {
42        "ArchStdEvent": "L1I_CACHE_REFILL"
43    },
44    {
45        "ArchStdEvent": "L1I_TLB_REFILL"
46    },
47    {
48        "ArchStdEvent": "L1D_CACHE_REFILL"
49    },
50    {
51        "ArchStdEvent": "L1D_CACHE"
52    },
53    {
54        "ArchStdEvent": "L1D_TLB_REFILL"
55    },
56    {
57        "ArchStdEvent": "L1I_CACHE"
58    },
59    {
60        "ArchStdEvent": "L2D_CACHE"
61    },
62    {
63        "ArchStdEvent": "L2D_CACHE_REFILL"
64    },
65    {
66        "ArchStdEvent": "L2D_CACHE_WB"
67    },
68    {
69        "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB",
70        "ArchStdEvent": "L1D_TLB",
71        "BriefDescription": "L1D TLB access"
72    },
73    {
74        "PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB",
75        "ArchStdEvent": "L1I_TLB"
76    },
77    {
78        "PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",
79        "EventCode": "0x34",
80        "EventName": "L2D_TLB_ACCESS",
81        "BriefDescription": "L2D TLB access"
82    },
83    {
84        "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",
85        "EventCode": "0x35",
86        "EventName": "L2I_TLB_ACCESS",
87        "BriefDescription": "L2I TLB access"
88    },
89    {
90        "PublicDescription": "Branch target buffer misprediction",
91        "EventCode": "0x102",
92        "EventName": "BTB_MIS_PRED",
93        "BriefDescription": "BTB misprediction"
94    },
95    {
96        "PublicDescription": "ITB miss",
97        "EventCode": "0x103",
98        "EventName": "ITB_MISS",
99        "BriefDescription": "ITB miss"
100    },
101    {
102        "PublicDescription": "DTB miss",
103        "EventCode": "0x104",
104        "EventName": "DTB_MISS",
105        "BriefDescription": "DTB miss"
106    },
107    {
108        "PublicDescription": "Level 1 data cache late miss",
109        "EventCode": "0x105",
110        "EventName": "L1D_CACHE_LATE_MISS",
111        "BriefDescription": "L1D cache late miss"
112    },
113    {
114        "PublicDescription": "Level 1 data cache prefetch request",
115        "EventCode": "0x106",
116        "EventName": "L1D_CACHE_PREFETCH",
117        "BriefDescription": "L1D cache prefetch"
118    },
119    {
120        "PublicDescription": "Level 2 data cache prefetch request",
121        "EventCode": "0x107",
122        "EventName": "L2D_CACHE_PREFETCH",
123        "BriefDescription": "L2D cache prefetch"
124    },
125    {
126        "PublicDescription": "Level 1 stage 2 TLB refill",
127        "EventCode": "0x111",
128        "EventName": "L1_STAGE2_TLB_REFILL",
129        "BriefDescription": "L1 stage 2 TLB refill"
130    },
131    {
132        "PublicDescription": "Page walk cache level-0 stage-1 hit",
133        "EventCode": "0x112",
134        "EventName": "PAGE_WALK_L0_STAGE1_HIT",
135        "BriefDescription": "Page walk, L0 stage-1 hit"
136    },
137    {
138        "PublicDescription": "Page walk cache level-1 stage-1 hit",
139        "EventCode": "0x113",
140        "EventName": "PAGE_WALK_L1_STAGE1_HIT",
141        "BriefDescription": "Page walk, L1 stage-1 hit"
142    },
143    {
144        "PublicDescription": "Page walk cache level-2 stage-1 hit",
145        "EventCode": "0x114",
146        "EventName": "PAGE_WALK_L2_STAGE1_HIT",
147        "BriefDescription": "Page walk, L2 stage-1 hit"
148    },
149    {
150        "PublicDescription": "Page walk cache level-1 stage-2 hit",
151        "EventCode": "0x115",
152        "EventName": "PAGE_WALK_L1_STAGE2_HIT",
153        "BriefDescription": "Page walk, L1 stage-2 hit"
154    },
155    {
156        "PublicDescription": "Page walk cache level-2 stage-2 hit",
157        "EventCode": "0x116",
158        "EventName": "PAGE_WALK_L2_STAGE2_HIT",
159        "BriefDescription": "Page walk, L2 stage-2 hit"
160    }
161]
162