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/freebsd/sys/dev/clk/rockchip/
H A Drk3399_cru.c58 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7),
59 GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6),
60 GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5),
61 GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4),
62 GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3),
63 GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2),
64 GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1),
65 GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0),
69 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),
70 GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6),
[all …]
H A Drk3288_cru.c78 #define GATE(_idx, _clkname, _pname, _o, _s) \ macro
89 GATE(0, "sclk_acc_efuse", "xin24m", 0, 12),
90 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11),
91 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
92 GATE(0, "gpll_ddr", "gpll", 0, 9),
93 GATE(0, "dpll_ddr", "dpll", 0, 8),
94 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0, 7),
95 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_s", 0, 5),
96 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_s", 0, 4),
97 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 3),
[all …]
H A Drk3568_cru.c815 GATE(0, "sclk_core_src", "sclk_core_src_c", 0, 5),
818 GATE(0, "atclk_core", "atclk_core_div", 0, 8),
819 GATE(0, "gicclk_core", "gicclk_core_div", 0, 9),
820 GATE(0, "pclk_core_pre", "pclk_core_pre_div", 0, 10),
821 GATE(0, "periphclk_core_pre", "periphclk_core_pre_div", 0, 11),
837 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9),
838 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10),
839 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11),
840 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12),
847 GATE(CLK_GPU_SRC, "clk_gpu_src", "clk_gpu_pre_c", 2, 0),
[all …]
H A Drk3328_cru.c253 GATE(0, "core_apll_clk", "apll", 0, 0),
254 GATE(0, "core_dpll_clk", "dpll", 0, 1),
255 GATE(0, "core_gpll_clk", "gpll", 0, 2),
262 GATE(SCLK_WIFI, "sclk_wifi", "sclk_wifi_c", 0, 10),
263 GATE(SCLK_RTC32K, "clk_rtc32k", "clk_rtc32k_c", 0, 11),
264 GATE(0, "core_npll_clk", "npll", 0, 12),
269 GATE(0, "clk_i2s0_div", "clk_i2s0_div_c", 1, 1),
270 GATE(0, "clk_i2s0_frac", "clk_i2s0_frac_f", 1, 2),
271 GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 1, 3),
272 GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 1, 4),
[all …]
H A Drk3568_pmucru.c163 GATE(XIN_OSC0_DIV, "xin_osc0_div", "xin_osc0_div_div", 0, 0),
164 GATE(CLK_RTC_32K, "clk_rtc_32k", "clk_rtc_32k_mux", 0, 1),
165 GATE(PCLK_PDPMU, "pclk_pdpmu", "pclk_pdpmu_pre", 0, 2),
166 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 6),
167 GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 7),
170 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 1, 0),
171 GATE(CLK_I2C0, "clk_i2c0", "clk_i2c0_div", 1, 1),
172 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 1, 2),
173 GATE(CLK_UART0_DIV, "sclk_uart0_div", "sclk_uart0_div_div", 1, 3),
174 GATE(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_frac_div", 1, 4),
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c76 #define GATE(_id, cname, plist, _idx) \ macro
214 /* GATE(CPU, "cpu", "clk_m", L(0)), */
215 GATE(ISPB, "ispb", "clk_m", L(3)),
216 GATE(RTC, "rtc", "clk_s", L(4)),
217 GATE(TIMER, "timer", "clk_m", L(5)),
218 GATE(UARTA, "uarta", "pc_uarta" , L(6)),
219 GATE(UARTB, "uartb", "pc_uartb", L(7)),
220 GATE(VFIR, "vfir", "pc_vfir", L(7)),
221 /* GATE(GPIO, "gpio", "clk_m", L(8)), */
222 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c71 #define GATE(_id, cname, plist, _idx) \ macro
309 GATE(ISPB, "ispb", "clk_m", L(3)),
310 GATE(RTC, "rtc", "clk_s", L(4)),
311 GATE(TIMER, "timer", "clk_m", L(5)),
312 GATE(UARTA, "uarta", "pc_uarta" , L(6)),
313 GATE(UARTB, "uartb", "pc_uartb", L(7)),
314 GATE(GPIO, "gpio", "clk_m", L(8)),
315 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
316 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)),
317 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)),
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dgate.txt1 Binding for Texas Instruments gate clock.
4 quite much similar to the basic gate-clock [2], however,
11 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
16 "ti,gate-clock" - basic gate clock
17 "ti,wait-gate-clock" - gate clock which waits until clock is active before
19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
20 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
21 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
24 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
26 "ti,composite-gate-clock" - composite gate clock, to be part of composite
[all …]
/freebsd/sys/arm/mv/clk/
H A Dperiph.h92 .clk_def.full_dd.gate.clkdef.name = _name, \
93 .clk_def.full_dd.gate.offset = CLK_DIS, \
94 .clk_def.full_dd.gate.shift = _gate_shift, \
95 .clk_def.full_dd.gate.on_value = 0, \
96 .clk_def.full_dd.gate.off_value = 1, \
97 .clk_def.full_dd.gate.mask = 0x1, \
98 .clk_def.full_dd.gate.gate_flags = 0x0 \
126 .clk_def.full_d.gate.clkdef.name = _name, \
127 .clk_def.full_d.gate.offset = CLK_DIS, \
128 .clk_def.full_d.gate.shift = _gate_shift, \
[all …]
H A Dperiph_clk_mux_gate.c55 * gate (enable or disable clock).
64 struct clk_gate_def *gate; in a37x0_periph_register_mux_gate() local
70 gate = &device_def->clk_def.mux_gate.gate; in a37x0_periph_register_mux_gate()
94 a37x0_periph_set_props(&gate->clkdef, &mux->clkdef.name, 1); in a37x0_periph_register_mux_gate()
95 error = a37x0_periph_create_gate(clkdom, gate, in a37x0_periph_register_mux_gate()
107 * gate -> fixed2 (freq/2).
116 struct clk_gate_def *gate; in a37x0_periph_register_mux_gate_fixed() local
122 gate = &device_def->clk_def.mux_gate_fixed.gate; in a37x0_periph_register_mux_gate_fixed()
146 a37x0_periph_set_props(&gate->clkdef, &mux->clkdef.name, 1); in a37x0_periph_register_mux_gate_fixed()
147 error = a37x0_periph_create_gate(clkdom, gate, in a37x0_periph_register_mux_gate_fixed()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsprd,sc9860-clk.yaml17 - sprd,sc9860-agcp-gate
19 - sprd,sc9860-aon-gate
21 - sprd,sc9860-apahb-gate
22 - sprd,sc9860-apapb-gate
25 - sprd,sc9860-cam-gate
27 - sprd,sc9860-disp-gate
30 - sprd,sc9860-pmu-gate
32 - sprd,sc9860-vsp-gate
61 - sprd,sc9860-agcp-gate
62 - sprd,sc9860-aon-gate
[all …]
H A Dsprd,sc9860-clk.txt6 - "sprd,sc9860-pmu-gate"
10 - "sprd,sc9860-apahb-gate"
11 - "sprd,sc9860-aon-gate"
13 - "sprd,sc9860-agcp-gate"
16 - "sprd,sc9860-vsp-gate"
18 - "sprd,sc9860-cam-gate"
20 - "sprd,sc9860-disp-gate"
21 - "sprd,sc9860-apapb-gate"
43 pmu_gate: pmu-gate {
44 compatible = "sprd,sc9860-pmu-gate";
H A Dsprd,ums512-clk.yaml18 - sprd,ums512-apahb-gate
21 - sprd,ums512-pmu-gate
26 - sprd,ums512-aon-gate
27 - sprd,ums512-audcpapb-gate
28 - sprd,ums512-audcpahb-gate
31 - sprd,ums512-mm-gate-clk
32 - sprd,ums512-apapb-gate
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi302 compatible = "altr,socfpga-gate-clk";
304 clk-gate = <0x60 0>;
316 compatible = "altr,socfpga-gate-clk";
319 clk-gate = <0x60 1>;
324 compatible = "altr,socfpga-gate-clk";
331 compatible = "altr,socfpga-gate-clk";
334 clk-gate = <0x60 2>;
339 compatible = "altr,socfpga-gate-clk";
342 clk-gate = <0x60 3>;
347 compatible = "altr,socfpga-gate
[all...]
/freebsd/sys/arm/mv/
H A Dmv_cp110_clock.c97 CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0)
98 CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1)
99 /* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */
100 CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3)
101 CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4)
102 CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5)
103 CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6)
104 CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7)
105 CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8)
106 CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9)
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mq_ccm.c168 GATE(IMX8MQ_ARM_PLL_OUT, "arm_pll_out", "arm_pll_bypass", 0x28, 21),
169 GATE(IMX8MQ_GPU_PLL_OUT, "gpu_pll_out", "gpu_pll_bypass", 0x18, 21),
170 GATE(IMX8MQ_VPU_PLL_OUT, "vpu_pll_out", "vpu_pll_bypass", 0x20, 21),
171 GATE(IMX8MQ_AUDIO_PLL1_OUT, "audio_pll1_out", "audio_pll1_bypass", 0x0, 21),
172 GATE(IMX8MQ_AUDIO_PLL2_OUT, "audio_pll2_out", "audio_pll2_bypass", 0x8, 21),
173 GATE(IMX8MQ_VIDEO_PLL1_OUT, "video_pll1_out", "video_pll1_bypass", 0x10, 21),
175 GATE(IMX8MQ_SYS1_PLL_40M_CG, "sys1_pll_40m_cg", "sys1_pll_out", 0x30, 9),
176 GATE(IMX8MQ_SYS1_PLL_80M_CG, "sys1_pll_80m_cg", "sys1_pll_out", 0x30, 11),
177 GATE(IMX8MQ_SYS1_PLL_100M_CG, "sys1_pll_100m_cg", "sys1_pll_out", 0x30, 13),
178 GATE(IMX8MQ_SYS1_PLL_133M_CG, "sys1_pll_133m_cg", "sys1_pll_out", 0x30, 15),
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra186-clock.h350 /** @brief output of gate CLK_ENB_FUSE */
354 * @details output of gate CLK_ENB_GPU. This output connects to the GPU
360 /** @brief output of gate CLK_ENB_PCIE */
364 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
366 /** @brief output of gate CLK_ENB_PCIERX0*/
368 /** @brief output of gate CLK_ENB_PCIERX1*/
370 /** @brief output of gate CLK_ENB_PCIERX2*/
372 /** @brief output of gate CLK_ENB_PCIERX3*/
374 /** @brief output of gate CLK_ENB_PCIERX4*/
376 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
[all …]
H A Dtegra234-clock.h14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
20 /** @brief output of gate CLK_ENB_APB2APE */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
34 /** @brief output of gate CLK_ENB_CAN2_HOST */
46 /** @brief output of gate CLK_ENB_DPAUX */
85 /** @brief output of gate CLK_ENB_EQOS_RX */
97 /** @brief output of gate CLK_ENB_FUSE */
154 /** @brief output of gate CLK_ENB_MIPI_CAL */
158 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-gate.txt1 An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected
3 some kind of operation to access the i2c bus past the arbitrator/gate, but
7 Common i2c gate properties.
9 - i2c-gate child node
11 Required properties for the i2c-gate child node:
15 Optional properties for i2c-gate child node:
23 Kasei ak8975 compass behind a gate.
32 i2c-gate {
/freebsd/sys/dev/clk/allwinner/
H A Dccu_d1.c205 27, /* gate */
218 27, /* gate */
232 27, /* gate */
245 0, /* gate */
257 0, /* gate */
280 27, /* gate */
294 0, /* gate */
317 27, /* gate */
331 0, /* gate */
354 27, /* gate */
[all …]
H A Dccu_a31.c249 31, /* gate */
261 31, /* gate */
297 31, 28, 1000, /* gate, lock, lock retries */
318 31, 28, 1000, /* gate, lock, lock retries */
332 31, /* gate */
345 31, /* gate */
365 31, 28, 1000, /* gate, lock, lock retries */
387 31, 28, 1000, /* gate, lock, lock retries */
402 31, /* gate */
412 31, 28, 1000, /* gate, lock, lock retries */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3xxx-clocks.dtsi33 compatible = "ti,gate-clock";
238 compatible = "ti,gate-clock";
355 compatible = "ti,gate-clock";
514 compatible = "ti,gate-clock";
548 compatible = "ti,gate-clock";
576 compatible = "ti,gate-clock";
594 compatible = "ti,gate-clock";
617 clkout2_src_gate_ck: clock-clkout2-src-gate@7 {
620 compatible = "ti,composite-no-wait-gate-clock";
754 gpt10_gate_fck: clock-gpt10-gate-fck@11 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml43 - description: m2p0 channel gate clock
44 - description: m2p1 channel gate clock
45 - description: m2p2 channel gate clock
46 - description: m2p3 channel gate clock
47 - description: m2p4 channel gate clock
48 - description: m2p5 channel gate clock
49 - description: m2p6 channel gate clock
50 - description: m2p7 channel gate clock
51 - description: m2p8 channel gate clock
52 - description: m2p9 channel gate clock
/freebsd/sys/x86/include/
H A Dsegments.h97 * Gate descriptors (e.g. indirect descriptors)
100 unsigned gd_looffset:16; /* gate offset (lsb) */
101 unsigned gd_selector:16; /* gate segment selector */
107 unsigned gd_hioffset:16; /* gate offset (msb) */
119 * Gate descriptors (e.g. indirect descriptors, trap, interrupt etc. 128 bit)
123 uint64_t gd_looffset:16; /* gate offset (lsb) */
124 uint64_t gd_selector:16; /* gate segment selector */
130 uint64_t gd_hioffset:48; /* gate offset (msb) */
143 /* system segments and gate types */
148 #define SDT_SYS286CGT 4 /* system 286 call gate */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.

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