Lines Matching full:gate

78 #define	GATE(_idx, _clkname, _pname, _o, _s)				\  macro
89 GATE(0, "sclk_acc_efuse", "xin24m", 0, 12),
90 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11),
91 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
92 GATE(0, "gpll_ddr", "gpll", 0, 9),
93 GATE(0, "dpll_ddr", "dpll", 0, 8),
94 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0, 7),
95 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_s", 0, 5),
96 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_s", 0, 4),
97 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 3),
98 GATE(0, "gpll_core", "gpll", 0, 2),
99 GATE(0, "apll_core", "apll", 0, 1),
103 GATE(0, "uart3_frac", "uart3_frac_s", 1, 15),
104 GATE(0, "uart3_src", "uart3_src_s", 1, 14),
105 GATE(0, "uart2_frac", "uart2_frac_s", 1, 13),
106 GATE(0, "uart2_src", "uart2_src_s", 1, 12),
107 GATE(0, "uart1_frac", "uart1_frac_s", 1, 11),
108 GATE(0, "uart1_src", "uart1_src_s", 1, 10),
109 GATE(0, "uart0_frac", "uart0_frac_s", 1, 9),
110 GATE(0, "uart0_src", "uart0_src_s", 1, 8),
111 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 1, 5),
112 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 1, 4),
113 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 1, 3),
114 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 1, 2),
115 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 1, 1),
116 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 1, 0),
119 GATE(0, "uart4_frac", "uart4_frac_s", 2, 13),
120 GATE(0, "uart4_src", "uart4_src_s", 2, 12),
121 GATE(SCLK_SPI2, "sclk_spi2", "sclk_spi2_s", 2, 11),
122 GATE(SCLK_SPI1, "sclk_spi1", "sclk_spi1_s", 2, 10),
123 GATE(SCLK_SPI0, "sclk_spi0", "sclk_spi0_s", 2, 9),
124 GATE(SCLK_SARADC, "sclk_saradc", "sclk_saradc_s", 2, 8),
125 GATE(SCLK_TSADC, "sclk_tsadc", "sclk_tsadc_s", 2, 7),
126 GATE(0, "hsadc_src", "hsadc_src_s", 2, 6),
127 GATE(0, "mac_pll_src", "mac_pll_src_s", 2, 5),
128 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_s", 2, 3),
129 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_s", 2, 2),
130 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 2, 1),
131 GATE(0, "aclk_peri_src", "aclk_peri_src_s", 2, 0),
134 GATE(SCLK_ISP_JPE, "sclk_isp_jpe", "sclk_isp_jpe_s", 3, 15),
135 GATE(SCLK_ISP, "sclk_isp", "sclk_isp_s", 3, 14),
136 GATE(SCLK_EDP, "sclk_edp", "sclk_edp_s", 3, 13),
137 GATE(SCLK_EDP_24M, "sclk_edp_24m", "sclk_edp_24m_s", 3, 12),
138 GATE(0, "aclk_vdpu", "aclk_vdpu_s", 3, 11),
139 GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_s", 3, 10),
140 GATE(0, "aclk_vepu", "aclk_vepu_s", 3, 9),
141 GATE(0, "vip_src", "vip_src_s", 3, 7),
143 GATE(0, "aclk_rga_pre", "aclk_rga_pre_s", 3, 5),
144 GATE(SCLK_RGA, "sclk_rga", "sclk_rga_s", 3, 4),
145 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_s", 3, 3),
146 GATE(0, "aclk_vio1", "aclk_vio1_s", 3, 2),
147 GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_s", 3, 1),
148 GATE(0, "aclk_vio0", "aclk_vio0_s", 3, 0),
152 GATE(0, "jtag", "ext_jtag", 4, 14),
153 GATE(0, "sclk_ddrphy1", "ddrphy", 4, 13),
154 GATE(0, "sclk_ddrphy0", "ddrphy", 4, 12),
155 GATE(0, "sclk_tspout", "sclk_tspout_s", 4, 11),
156 GATE(0, "sclk_tsp", "sclk_tsp_s", 4, 10),
157 GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 4, 9),
158 GATE(0, "spdif_8ch_frac", "spdif_8ch_frac_s", 4, 8),
159 GATE(0, "spdif_8ch_pre", "spdif_8ch_pre_s", 4, 7),
160 GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 4, 6),
161 GATE(0, "spdif_frac", "spdif_frac_s", 4, 5),
162 GATE(0, "spdif_pre", "spdif_pre_s", 4, 4),
163 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 4, 3),
164 GATE(0, "i2s_frac", "i2s_frac_s", 4, 2),
165 GATE(0, "i2s_src", "i2s_src_s", 4, 1),
166 GATE(SCLK_I2S0_OUT, "i2s0_clkout", "i2s0_clkout_s", 4, 1),
169 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 5, 15),
170 GATE(SCLK_USBPHY480M_SRC, "usbphy480m_src", "usbphy480m_src_s", 5, 14),
171 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 5, 13),
172 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 5, 12),
173 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 5, 11),
174 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 5, 10),
175 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 5, 9),
176 GATE(0, "pclk_pd_pmu", "pclk_pd_pmu_s", 5, 8),
177 GATE(SCLK_GPU, "sclk_gpu", "sclk_gpu_s", 5, 7),
178 GATE(SCLK_NANDC1, "sclk_nandc1", "sclk_nandc1_s", 5, 6),
179 GATE(SCLK_NANDC0, "sclk_nandc0", "sclk_nandc0_s", 5, 5),
180 GATE(SCLK_CRYPTO, "crypto", "crypto_s", 5, 4),
181 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 5, 3),
182 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 5, 2),
183 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 5, 1),
184 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 5, 0),
188 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 6, 15),
189 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 6, 14),
190 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 6, 13),
191 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 6, 12),
192 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 6, 11),
193 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 6, 9),
194 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 6, 8),
195 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 6, 7),
196 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 6, 6),
197 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 6, 5),
198 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 6, 4),
199 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 6, 3),
200 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 6, 2),
201 GATE(0, "pclk_peri_matrix", "pclk_peri", 6, 1),
202 GATE(0, "hclk_peri_matrix", "hclk_peri", 6, 0),
206 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 7, 15),
207 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 7, 14),
208 GATE(0, "hclk_mem", "hclk_peri", 7, 13),
209 GATE(0, "hclk_emem", "hclk_peri", 7, 12),
210 GATE(0, "aclk_peri_niu", "aclk_peri", 7, 11),
211 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 7, 10),
212 GATE(0, "hclk_usb_peri", "hclk_peri", 7, 9),
214 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 7, 7),
215 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 7, 6),
216 GATE(0, "pmu_hclk_otg0", "hclk_peri", 7, 5),
217 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 7, 4),
218 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 7, 3),
219 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 7, 2),
220 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 7, 1),
221 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 7, 0),
224 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 8, 12),
226 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 8, 8),
227 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 8, 7),
228 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 8, 6),
229 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 8, 5),
230 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 8, 4),
231 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 8, 3),
232 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 8, 2),
233 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 8, 1),
234 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 8, 0),
237 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 9, 1),
238 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 9, 0),
241 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 10, 15),
242 GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 10, 14),
243 GATE(0, "aclk_strc_sys", "aclk_cpu", 10, 13),
244 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 10, 12),
245 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 10, 11),
246 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 10, 10),
247 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 10, 9),
248 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 10, 8),
249 GATE(0, "sclk_intmem2", "aclk_cpu", 10, 7),
250 GATE(0, "sclk_intmem1", "aclk_cpu", 10, 6),
251 GATE(0, "sclk_intmem0", "aclk_cpu", 10, 5),
252 GATE(0, "aclk_intmem", "aclk_cpu", 10, 4),
253 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 10, 3),
254 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 10, 2),
255 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 10, 1),
256 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 10, 0),
259 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 11, 11),
260 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 11, 10),
261 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 11, 9),
262 GATE(0, "aclk_ccp", "aclk_cpu", 11, 8),
263 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 11, 7),
264 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 11, 6),
265 GATE(0, "nclk_ddrupctl1", "ddrphy", 11, 5),
266 GATE(0, "nclk_ddrupctl0", "ddrphy", 11, 4),
267 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 11, 3),
268 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 11, 2),
269 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 11, 1),
270 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 11, 0),
273 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 12, 11),
274 GATE(0, "cs_dbg", "pclk_dbg_pre", 12, 10),
275 GATE(0, "pclk_dbg", "pclk_dbg_pre", 12, 9),
276 GATE(0, "armcore0", "armcore0_s", 12, 8),
277 GATE(0, "armcore1", "armcore1_s", 12, 7),
278 GATE(0, "armcore2", "armcore2_s", 12, 6),
279 GATE(0, "armcore3", "armcore3_s", 12, 5),
280 GATE(0, "l2ram", "l2ram_s", 12, 4),
281 GATE(0, "aclk_core_m0", "aclk_core_m0_s", 12, 3),
282 GATE(0, "aclk_core_mp", "aclk_core_mp_s", 12, 2),
283 GATE(0, "atclk", "atclk_s", 12, 1),
284 GATE(0, "pclk_dbg_pre", "pclk_dbg_pre_s", 12, 0),
287 GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_s", 13, 15),
288 GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_s", 13, 14),
289 GATE(ACLK_HEVC, "aclk_hevc", "aclk_hevc_s", 13, 13),
290 GATE(0, "wii", "wifi_frac_s", 13, 12),
291 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 13, 11),
292 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 13, 10),
294 GATE(0, "c2c_host", "aclk_cpu_src", 13, 8),
295 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 13, 7),
296 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", 13, 6),
297 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 13, 5),
298 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 13, 4),
299 GATE(SCLK_EMMC, "sclk_emmc", "sclk_emmc_s", 13, 3),
300 GATE(SCLK_SDIO1, "sclk_sdio1", "sclk_sdio1_s", 13, 2),
301 GATE(SCLK_SDIO0, "sclk_sdio0", "sclk_sdio0_s", 13, 1),
302 GATE(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_s", 13, 0),
305 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 14, 12),
306 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 14, 11),
307 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 14, 8),
308 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 14, 7),
309 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 14, 6),
310 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 14, 5),
311 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 14, 4),
312 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 14, 3),
313 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 14, 2),
314 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 14, 1),
317 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 15, 15),
318 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 15, 14),
319 GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 15, 13),
320 GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 15, 12),
321 GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 15, 11),
322 GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 15, 10),
323 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio",15, 9),
324 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 15, 8),
325 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 15, 7),
326 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 15, 6),
327 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 15, 5),
329 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 15, 3),
330 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 15, 2),
331 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 15, 1),
332 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 15, 0),
335 GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 16, 11),
336 GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 16, 10),
337 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 16, 9),
338 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 16, 8),
339 GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 16, 7),
340 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 16, 6),
341 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 16, 5),
342 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 16, 4),
343 GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 16, 3),
344 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 16, 2),
345 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 16, 1),
346 GATE(0, "pclk_vip_in", "ext_vip", 16, 0),
349 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 17, 4),
350 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 17, 3),
351 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 17, 2),
352 GATE(0, "pclk_intmem1", "pclk_pd_pmu", 17, 1),
353 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 17, 0),
356 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 18, 0),