Lines Matching full:gate
815 GATE(0, "sclk_core_src", "sclk_core_src_c", 0, 5),
818 GATE(0, "atclk_core", "atclk_core_div", 0, 8),
819 GATE(0, "gicclk_core", "gicclk_core_div", 0, 9),
820 GATE(0, "pclk_core_pre", "pclk_core_pre_div", 0, 10),
821 GATE(0, "periphclk_core_pre", "periphclk_core_pre_div", 0, 11),
837 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9),
838 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10),
839 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11),
840 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12),
847 GATE(CLK_GPU_SRC, "clk_gpu_src", "clk_gpu_pre_c", 2, 0),
849 GATE(PCLK_GPU_PRE, "pclk_gpu_pre", "pclk_gpu_pre_div", 2, 2),
850 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_c", 2, 3),
853 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 2, 6),
854 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 2, 7),
855 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 2, 8),
856 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", 2, 9),
858 GATE(ACLK_GPU_PRE, "aclk_gpu_pre", "aclk_gpu_pre_div", 2, 11),
862 GATE(CLK_NPU_SRC, "clk_npu_src", "clk_npu_src_c", 3, 0),
863 GATE(CLK_NPU_NP5, "clk_npu_np5", "clk_npu_np5_c", 3, 1),
864 GATE(HCLK_NPU_PRE, "hclk_npu_pre", "hclk_npu_pre_div", 3, 2),
865 GATE(PCLK_NPU_PRE, "pclk_npu_pre", "pclk_npu_pre_div", 3, 3),
867 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 3, 4),
870 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 3, 7),
871 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 3, 8),
872 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 3, 9),
873 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 3, 10),
874 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft",3, 11),
875 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", 3, 12),
880 GATE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", "clk_ddrphy1x_src_c", 4, 0),
882 GATE(CLK_MSCH, "clk_msch", "clk_msch_div", 4, 2),
895 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", 4, 15),
898 GATE(ACLK_GIC_AUDIO, "aclk_gic_audio", "aclk_gic_audio_sel", 5, 0),
899 GATE(HCLK_GIC_AUDIO, "hclk_gic_audio", "hclk_gic_audio_sel", 5, 1),
902 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", 5, 4),
905 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", 5, 7),
906 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 5, 8),
907 GATE(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", "dclk_sdmmc_buffer_sel", 5, 9),
908 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 5, 10),
909 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 5, 11),
910 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 5, 12),
911 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 5, 13),
912 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 5, 14),
913 GATE(MCLK_PDM, "mclk_pdm", "mclk_pdm_sel", 5, 15),
916 GATE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_src_c", 6, 0),
917 GATE(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_frac_div", 6, 1),
918 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 6, 2),
919 GATE(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", "i2s0_mclkout_tx_sel", 6, 3),
920 GATE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_src_c", 6, 4),
921 GATE(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_frac_div", 6, 5),
922 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 6, 6),
923 GATE(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", "i2s0_mclkout_rx_sel", 6, 7),
924 GATE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_src_c", 6, 8),
925 GATE(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_frac_div", 6, 9),
926 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 6, 10),
927 GATE(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", "i2s1_mclkout_tx_sel", 6, 11),
928 GATE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_src_c", 6, 12),
929 GATE(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_frac_div", 6, 13),
930 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 6, 14),
931 GATE(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", "i2s1_mclkout_rx_sel", 6, 15),
934 GATE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "clk_i2s2_2ch_src_c", 7, 0),
935 GATE(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_frac_div", 7, 1),
936 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 7, 2),
937 GATE(I2S2_MCLKOUT, "i2s2_mclkout", "i2s2_mclkout_sel", 7, 3),
938 GATE(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_src_c", 7, 4),
939 GATE(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_frac_div", 7, 5),
940 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 7, 6),
941 GATE(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", "i2s3_mclkout_tx_sel", 7, 7),
942 GATE(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_src_div", 7, 8),
943 GATE(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_frac_div", 7, 9),
944 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 7, 10),
945 GATE(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", "i2s3_mclkout_rx_sel", 7, 11),
946 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 7, 12),
947 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 7, 13),
948 GATE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", "mclk_spdif_8ch_src_c", 7, 14),
949 GATE(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_frac_div", 7, 15),
952 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 8, 0),
953 GATE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", "sclk_audpwm_src_c", 8, 1),
954 GATE(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_frac_frac", 8, 2),
955 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 8, 3),
956 GATE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", "clk_acdcdig_i2c_sel", 8, 4),
957 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 8, 5),
958 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 8, 6),
959 GATE(ACLK_SECURE_FLASH, "aclk_secure_flash", "aclk_secure_flash_sel", 8, 7),
960 GATE(HCLK_SECURE_FLASH, "hclk_secure_flash", "hclk_secure_flash_sel", 8, 8),
963 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 8, 11),
964 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 8, 12),
965 GATE(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", "clk_crypto_ns_core_sel", 8, 13),
966 GATE(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", "clk_crypto_ns_pka_sel", 8, 14),
967 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 8, 15),
970 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 9, 0),
971 GATE(NCLK_NANDC, "nclk_nandc", "nclk_nandc_sel", 9, 1),
972 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 9, 2),
973 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 9, 3),
974 GATE(SCLK_SFC, "sclk_sfc", "sclk_sfc_sel", 9, 4),
975 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 9, 5),
976 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 9, 6),
977 GATE(BCLK_EMMC, "bclk_emmc", "bclk_emmc_sel", 9, 7),
978 GATE(CCLK_EMMC, "cclk_emmc", "cclk_emmc_sel", 9, 8),
979 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 9, 9),
980 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", 9, 10),
981 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", 9, 11),
985 GATE(ACLK_PIPE, "aclk_pipe", "aclk_pipe_sel", 10, 0),
986 GATE(PCLK_PIPE, "pclk_pipe", "pclk_pipe_div", 10, 1),
989 GATE(CLK_XPCS_EEE, "clk_xpcs_eee", "clk_xpcs_eee_sel", 10, 4),
993 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 10, 8),
994 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 10, 9),
995 GATE(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_sel", 10, 10),
997 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 10, 12),
998 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 10, 13),
999 GATE(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_sel", 10, 14),
1003 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 11, 0),
1004 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "clk_gpll_div_20m", 11, 1),
1005 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "clk_cpll_div_50m", 11, 2),
1007 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 11, 4),
1008 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "clk_gpll_div_20m", 11, 5),
1009 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "clk_cpll_div_50m", 11, 6),
1011 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 11, 8),
1012 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "clk_gpll_div_20m", 11, 9),
1013 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "clk_cpll_div_50m", 11, 10),
1018 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 12, 0),
1019 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 12, 1),
1020 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 12, 2),
1021 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 12, 3),
1022 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 12, 4),
1025 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 12, 8),
1026 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 12, 9),
1027 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 12, 10),
1028 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 12, 11),
1029 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 12, 12),
1034 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 13, 0),
1035 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 13, 1),
1036 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 13, 2),
1037 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 13, 3),
1038 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 13, 4),
1040 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 13, 6),
1052 GATE(ACLK_PERIMID, "aclk_perimid", "aclk_perimid_sel", 14, 0),
1053 GATE(HCLK_PERIMID, "hclk_perimid", "hclk_perimid_sel", 14, 1),
1057 GATE(ACLK_PHP, "aclk_php", "aclk_php_sel", 14, 8),
1058 GATE(HCLK_PHP, "hclk_php", "hclk_php_sel", 14, 9),
1059 GATE(PCLK_PHP, "pclk_php", "pclk_php_div", 14, 10),
1066 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 15, 0),
1067 GATE(CLK_SDMMC0, "clk_sdmmc0", "clk_sdmmc0_sel", 15, 1),
1068 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 15, 2),
1069 GATE(CLK_SDMMC1, "clk_sdmmc1", "clk_sdmmc1_sel", 15, 3),
1070 GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_sel", 15, 4),
1071 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 15, 5),
1072 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 15, 6),
1073 GATE(CLK_MAC0_2TOP, "clk_mac0_2top", "clk_mac0_2top_sel", 15, 7),
1074 GATE(CLK_MAC0_OUT, "clk_mac0_out", "clk_mac0_out_sel", 15, 8),
1076 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 15, 12),
1080 GATE(ACLK_USB, "aclk_usb", "aclk_usb_sel", 16, 0),
1081 GATE(HCLK_USB, "hclk_usb", "hclk_usb_sel", 16, 1),
1082 GATE(PCLK_USB, "pclk_usb", "pclk_usb_div", 16, 2),
1088 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 16, 12),
1089 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 16, 13),
1090 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 16, 14),
1091 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 16, 15),
1094 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 17, 0),
1095 GATE(CLK_SDMMC2, "clk_sdmmc2", "clk_sdmmc2_sel", 17, 1),
1096 GATE(CLK_GMAC1_PTP_REF, "clK_gmac1_ptp_ref", "clk_gmac1_ptp_ref_sel", 17, 2),
1097 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 17, 3),
1098 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 17, 4),
1099 GATE(CLK_MAC1_2TOP, "clk_mac1_2top", "clk_mac1_2top_sel", 17, 5),
1100 GATE(CLK_MAC1_OUT, "clk_mac1_out", "clk_mac1_out_sel", 17, 6),
1102 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 17, 10),
1106 GATE(ACLK_VI, "aclk_vi", "aclk_vi_sel", 18, 0),
1107 GATE(HCLK_VI, "hclk_vi", "hclk_vi_div", 18, 1),
1108 GATE(PCLK_VI, "pclk_vi", "pclk_vi_div", 18, 2),
1113 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 18, 9),
1114 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 18, 10),
1115 GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap1_sel", 18, 11),
1119 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 19, 0),
1120 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 19, 1),
1121 GATE(CLK_ISP, "clk_isp", "clk_isp_c", 19, 2),
1123 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 19, 4),
1125 GATE(CLK_CIF_OUT, "clk_cif_out", "clk_cif_out_c", 19, 8),
1126 GATE(CLK_CAM0_OUT, "clk_cam0_out", "clk_cam0_out_c", 19, 9),
1127 GATE(CLK_CAM1_OUT, "clk_cam1_out", "clk_cam1_out_c", 19, 9),
1132 GATE(ACLK_VO, "aclk_vo", "aclk_vo_sel", 20, 0),
1133 GATE(HCLK_VO, "hclk_vo", "hclk_vo_div", 20, 1),
1134 GATE(PCLK_VO, "pclk_vo", "pclk_vo_div", 20, 2),
1138 GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 20, 6),
1140 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 20, 8),
1141 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 20, 9),
1142 GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_c", 20, 10),
1143 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_c", 20, 11),
1144 GATE(DCLK_VOP2, "dclk_vop2", "dclk_vop2_c", 20, 12),
1145 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 20, 13),
1149 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 21, 0),
1150 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 21, 1),
1151 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 21, 2),
1152 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 21, 3),
1153 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 21, 4),
1154 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 21, 5),
1155 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 21, 6),
1156 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 21, 7),
1157 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 21, 8),
1158 GATE(CLK_EDP_200M, "clk_edp_200m", "clk_edp_200m_sel", 21, 9),
1162 GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 22, 0),
1163 GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre_c", 22, 1),
1166 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 22, 4),
1167 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 22, 5),
1169 GATE(PCLK_RGA_PRE, "pclk_rga_pre", "pclk_rga_pre_div", 22, 12),
1171 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 22, 14),
1172 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 22, 15),
1175 GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_sel", 23, 0),
1176 GATE(HCLK_RGA_PRE, "hclk_rga_pre", "hclk_rga_pre_div", 23, 1),
1179 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 23, 4),
1180 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 23, 5),
1181 GATE(CLK_RGA_CORE, "clk_rga_core", "clk_rga_core_sel", 23, 6),
1182 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 23, 7),
1183 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 23, 8),
1184 GATE(CLK_IEP_CORE, "clk_iep_core", "clk_iep_core_sel", 23, 9),
1185 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 23, 10),
1186 GATE(DCLK_EBC, "dclk_ebc", "dclk_ebc_sel", 23, 11),
1187 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 23, 12),
1188 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 23, 13),
1189 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 23, 14),
1190 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 23, 15),
1193 GATE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", "aclk_rkvenc_pre_c", 24, 0),
1194 GATE(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "hclk_rkvenc_pre_div", 24, 1),
1199 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 24, 6),
1200 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 24, 7),
1201 GATE(CLK_RKVENC_CORE, "clk_rkvenc_core", "clk_rkvenc_core_c", 24, 8),
1205 GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_pre_c", 25, 0),
1206 GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "hclk_rkvdec_pre_div", 25, 1),
1209 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 25, 4),
1210 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 25, 5),
1211 GATE(CLK_RKVDEC_CA, "clk_rkvdec_ca", "clk_rkvdec_ca_c", 25, 6),
1212 GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "clk_rkvdec_core_c", 25, 7),
1213 GATE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", "clk_rkvdec_hevc_ca_c", 25, 8),
1217 GATE(ACLK_BUS, "aclk_bus", "aclk_bus_sel", 26, 0),
1218 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_sel", 26, 1),
1221 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 26, 4),
1222 GATE(CLK_TSADC_TSEN, "clk_tsadc_tsen", "clk_tsadc_tsen_c", 26, 5),
1223 GATE(CLK_TSADC, "clk_tsadc", "clk_tsadc_div", 26, 6),
1224 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 26, 7),
1225 GATE(CLK_SARADC, "clk_saradc", "xin24m", 26, 8),
1226 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 26, 9),
1227 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 26, 10),
1228 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 26, 11),
1229 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", 26, 12),
1230 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 26, 13),
1231 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 26, 14),
1239 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 27, 5),
1240 GATE(CLK_CAN0, "clk_can0", "clk_can0_c", 27, 6),
1241 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 27, 7),
1242 GATE(CLK_CAN1, "clk_can1", "clk_can1_c", 27, 8),
1243 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 27, 9),
1244 GATE(CLK_CAN2, "clk_can2", "clk_can2_c", 27, 10),
1246 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 27, 12),
1247 GATE(CLK_UART1_SRC, "clk_uart1_src", "clk_uart1_src_c", 27, 13),
1248 GATE(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_frac_frac", 27, 14),
1249 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_sel", 27, 15),
1252 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 28, 0),
1253 GATE(CLK_UART2_SRC, "clk_uart2_src", "clk_uart2_src_c", 28, 1),
1254 GATE(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_frac_frac", 28, 2),
1255 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_sel", 28, 3),
1256 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 28, 4),
1257 GATE(CLK_UART3_SRC, "clk_uart3_src", "clk_uart3_src_c", 28, 5),
1258 GATE(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_frac_frac", 28, 6),
1259 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_sel", 28, 7),
1260 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 28, 8),
1261 GATE(CLK_UART4_SRC, "clk_uart4_src", "clk_uart4_src_c", 28, 9),
1262 GATE(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_frac_frac", 28, 10),
1263 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_sel", 28, 11),
1264 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 28, 12),
1265 GATE(CLK_UART5_SRC, "clk_uart5_src", "clk_uart5_src_c", 28, 13),
1266 GATE(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_frac_frac", 28, 14),
1267 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_sel", 28, 15),
1270 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 29, 0),
1271 GATE(CLK_UART6_SRC, "clk_uart6_src", "clk_uart6_src_c", 29, 1),
1272 GATE(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_frac_frac", 29, 2),
1273 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_sel", 29, 3),
1274 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 29, 4),
1275 GATE(CLK_UART7_SRC, "clk_uart7_src", "clk_uart7_src_c", 29, 5),
1276 GATE(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_frac_frac", 29, 6),
1277 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_sel", 29, 7),
1278 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 29, 8),
1279 GATE(CLK_UART8_SRC, "clk_uart8_src", "clk_uart8_src_c", 29, 9),
1280 GATE(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_frac_frac", 29, 10),
1281 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_sel", 29, 11),
1282 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 29, 12),
1283 GATE(CLK_UART9_SRC, "clk_uart9_src", "clk_uart9_src_c", 29, 13),
1284 GATE(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_frac_frac", 29, 14),
1285 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_sel", 29, 15),
1288 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 30, 0),
1289 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 30, 1),
1290 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 30, 2),
1291 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 30, 3),
1292 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 30, 4),
1293 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 30, 5),
1294 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 30, 6),
1295 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 30, 7),
1296 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 30, 8),
1297 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 30, 9),
1298 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 30, 10),
1299 GATE(CLK_SPI0, "clk_spi0", "clk_spi0_sel", 30, 11),
1300 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 30, 12),
1301 GATE(CLK_SPI1, "clk_spi1", "clk_spi1_sel", 30, 13),
1302 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 30, 14),
1303 GATE(CLK_SPI2, "clk_spi2", "clk_spi2_sel", 30, 15),
1306 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 31, 0),
1307 GATE(CLK_SPI3, "clk_spi3", "clk_spi3_sel", 31, 1),
1308 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 31, 2),
1309 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 31, 3),
1310 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 31, 4),
1311 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 31, 5),
1312 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 31, 6),
1313 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 31, 7),
1314 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 31, 8),
1315 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 31, 9),
1316 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 31, 10),
1317 GATE(CLK_PWM1, "clk_pwm1", "clk_pwm1_sel", 31, 11),
1318 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 31, 12),
1319 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 31, 13),
1320 GATE(CLK_PWM2, "clk_pwm2", "clk_pwm2_sel", 31, 14),
1321 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 31, 15),
1324 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 32, 0),
1325 GATE(CLK_PWM3, "clk_pwm3", "clk_pwm3_sel", 32, 1),
1326 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 32, 2),
1327 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 32, 3),
1328 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 32, 4),
1329 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 32, 5),
1330 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 32, 6),
1331 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 32, 7),
1332 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 32, 8),
1333 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 32, 9),
1334 GATE(CLK_I2C, "clk_i2c", "clk_i2c_sel", 32, 10),
1335 GATE(DBCLK_GPIO, "dbclk_gpio", "dbclk_gpio_sel", 32, 11),
1337 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", 32, 13),
1338 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", 32, 14),
1339 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 32, 15),
1342 GATE(ACLK_TOP_HIGH, "aclk_top_high", "aclk_top_high_sel", 33, 0),
1343 GATE(ACLK_TOP_LOW, "aclk_top_low", "aclk_top_low_sel", 33, 1),
1344 GATE(HCLK_TOP, "hclk_top", "hclk_top_sel", 33, 2),
1345 GATE(PCLK_TOP, "pclk_top", "pclk_top_sel", 33, 3),
1350 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 33, 8),
1351 GATE(CLK_OPTC_ARB, "clk_optc_arb", "clk_optc_arb_sel", 33, 9),
1354 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 33, 13),
1355 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 33, 14),
1356 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 33, 15),
1363 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 34, 4),
1364 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 34, 5),
1365 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 34, 6),
1370 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 34, 11),
1371 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 34, 12),
1372 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 34, 13),
1373 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 34, 14),
1377 GATE(0, "clk_gpll_div_400m", "clk_gpll_div_400m_div", 35, 0),
1378 GATE(0, "clk_gpll_div_300m", "clk_gpll_div_300m_div", 35, 1),
1379 GATE(0, "clk_gpll_div_200m", "clk_gpll_div_200m_div", 35, 2),
1380 GATE(0, "clk_gpll_div_150m", "clk_gpll_div_150m_div", 35, 3),
1381 GATE(0, "clk_gpll_div_100m", "clk_gpll_div_100m_div", 35, 4),
1382 GATE(0, "clk_gpll_div_75m", "clk_gpll_div_75m_div", 35, 5),
1383 GATE(0, "clk_gpll_div_20m", "clk_gpll_div_20m_div", 35, 6),
1384 GATE(CPLL_500M, "clk_cpll_div_500m", "clk_cpll_div_500m_div", 35, 7),
1385 GATE(CPLL_333M, "clk_cpll_div_333m", "clk_cpll_div_333m_div", 35, 8),
1386 GATE(CPLL_250M, "clk_cpll_div_250m", "clk_cpll_div_250m_div", 35, 9),
1387 GATE(CPLL_125M, "clk_cpll_div_125m", "clk_cpll_div_125m_div", 35, 10),
1388 GATE(CPLL_100M, "clk_cpll_div_100m", "clk_cpll_div_100m_div", 35, 11),
1389 GATE(CPLL_62P5M, "clk_cpll_div_62P5m", "clk_cpll_div_62P5m_div", 35, 12),
1390 GATE(CPLL_50M, "clk_cpll_div_50m", "clk_cpll_div_50m_div", 35, 13),
1391 GATE(CPLL_25M, "clk_cpll_div_25m", "clk_cpll_div_25m_div", 35, 14),
1392 GATE(0, "clk_osc0_div_750k", "clk_osc0_div_750k_div", 35, 15),