Lines Matching full:gate

58 	GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m",		0, 7),
59 GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6),
60 GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5),
61 GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4),
62 GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3),
63 GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2),
64 GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1),
65 GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0),
69 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),
70 GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6),
71 GATE(0, "atclk_core_b", "atclk_core_b_c", 1, 5),
72 GATE(0, "aclkm_core_b", "aclkm_core_b_c", 1, 4),
73 GATE(0, "clk_core_b_gpll_src", "gpll", 1, 3),
74 GATE(0, "clk_core_b_dpll_src", "dpll", 1, 2),
75 GATE(0, "clk_core_b_bpll_src", "bpll", 1, 1),
76 GATE(0, "clk_core_b_lpll_src", "lpll", 1, 0),
80 GATE(0, "npll_cs", "npll", 2, 10),
81 GATE(0, "gpll_cs", "gpll", 2, 9),
82 GATE(0, "cpll_cs", "cpll", 2, 8),
83 GATE(SCLK_CCI_TRACE, "clk_cci_trace", "clk_cci_trace_c", 2, 7),
84 GATE(0, "gpll_cci_trace", "gpll", 2, 6),
85 GATE(0, "cpll_cci_trace", "cpll", 2, 5),
86 GATE(0, "aclk_cci_pre", "aclk_cci_pre_c", 2, 4),
87 GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3),
88 GATE(0, "npll_aclk_cci_src", "npll", 2, 2),
89 GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1),
90 GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0),
94 GATE(0, "aclk_center", "aclk_center_c", 3, 7),
97 GATE(PCLK_DDR, "pclk_ddr", "pclk_ddr_c", 3, 4),
98 GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3),
99 GATE(0, "clk_ddrc_dpll_src", "dpll", 3, 2),
100 GATE(0, "clk_ddrc_bpll_src", "bpll", 3, 1),
101 GATE(0, "clk_ddrc_lpll_src", "lpll", 3, 0),
105 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11),
106 GATE(0, "clk_rga_core", "clk_rga_core_c", 4, 10),
107 GATE(0, "hclk_rga_pre", "hclk_rga_pre_c", 4, 9),
108 GATE(0, "aclk_rga_pre", "aclk_rga_pre_c", 4, 8),
109 GATE(0, "hclk_iep_pre", "hclk_iep_pre_c", 4, 7),
110 GATE(0, "aclk_iep_pre", "aclk_iep_pre_c", 4, 6),
111 GATE(SCLK_VDU_CA, "clk_vdu_ca", "clk_vdu_ca_c", 4, 5),
112 GATE(SCLK_VDU_CORE, "clk_vdu_core", "clk_vdu_core_c", 4, 4),
113 GATE(0, "hclk_vdu_pre", "hclk_vdu_pre_c", 4, 3),
114 GATE(0, "aclk_vdu_pre", "aclk_vdu_pre_c", 4, 2),
115 GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_c", 4, 1),
116 GATE(0, "aclk_vcodec_pre", "aclk_vcodec_pre_c", 4, 0),
120 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 5, 9),
121 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 5, 8),
122 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 5, 7),
123 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 5, 6),
124 GATE(SCLK_MAC, "clk_gmac", "clk_gmac_c", 5, 5),
125 GATE(PCLK_PERIHP, "pclk_perihp", "pclk_perihp_c", 5, 4),
126 GATE(HCLK_PERIHP, "hclk_perihp", "hclk_perihp_c", 5, 3),
127 GATE(ACLK_PERIHP, "aclk_perihp", "aclk_perihp_c", 5, 2),
128 GATE(0, "cpll_aclk_perihp_src", "cpll", 5, 1),
129 GATE(0, "gpll_aclk_perihp_src", "gpll", 5, 0),
133 GATE(SCLK_EMMC, "clk_emmc", "clk_emmc_c", 6, 14),
134 GATE(0, "cpll_aclk_emmc_src", "cpll", 6, 13),
135 GATE(0, "gpll_aclk_emmc_src", "gpll", 6, 12),
136 GATE(0, "pclk_gmac_pre", "pclk_gmac_pre_c", 6, 11),
137 GATE(0, "aclk_gmac_pre", "aclk_gmac_pre_c", 6, 10),
138 GATE(0, "cpll_aclk_gmac_src", "cpll", 6, 9),
139 GATE(0, "gpll_aclk_gmac_src", "gpll", 6, 8),
141 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6),
142 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5),
143 GATE(SCLK_HSICPHY, "clk_hsicphy", "clk_hsicphy_c", 6, 4),
144 GATE(0, "clk_pcie_core_cru", "clk_pcie_core_cru_c", 6, 3),
145 GATE(SCLK_PCIE_PM, "clk_pcie_pm", "clk_pcie_pm_c", 6, 2),
146 GATE(SCLK_SDMMC, "clk_sdmmc", "clk_sdmmc_c", 6, 1),
147 GATE(SCLK_SDIO, "clk_sdio", "clk_sdio_c", 6, 0),
151 GATE(FCLK_CM0S, "fclk_cm0s", "fclk_cm0s_c", 7, 9),
152 GATE(SCLK_CRYPTO1, "clk_crypto1", "clk_crypto1_c", 7, 8),
153 GATE(SCLK_CRYPTO0, "clk_crypto0", "clk_crypto0_c", 7, 7),
154 GATE(0, "cpll_fclk_cm0s_src", "cpll", 7, 6),
155 GATE(0, "gpll_fclk_cm0s_src", "gpll", 7, 5),
156 GATE(PCLK_PERILP0, "pclk_perilp0", "pclk_perilp0_c", 7, 4),
157 GATE(HCLK_PERILP0, "hclk_perilp0", "hclk_perilp0_c", 7, 3),
158 GATE(ACLK_PERILP0, "aclk_perilp0", "aclk_perilp0_c", 7, 2),
159 GATE(0, "cpll_aclk_perilp0_src", "cpll", 7, 1),
160 GATE(0, "gpll_aclk_perilp0_src", "gpll", 7, 0),
163 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", 8, 15),
164 GATE(0, "clk_spdif_frac", "clk_spdif_frac_c", 8, 14),
165 GATE(0, "clk_spdif_div", "clk_spdif_div_c", 8, 13),
166 GATE(SCLK_I2S_8CH_OUT, "clk_i2sout", "clk_i2sout_c", 8, 12),
167 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", 8, 11),
168 GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_c", 8, 10),
169 GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 8, 9),
170 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", 8, 8),
171 GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_c", 8, 7),
172 GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 8, 6),
173 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", 8, 5),
174 GATE(0, "clk_i2s0_frac","clk_i2s0_frac_c", 8, 4),
175 GATE(0, "clk_i2s0_div","clk_i2s0_div_c", 8, 3),
176 GATE(PCLK_PERILP1, "pclk_perilp1", "pclk_perilp1_c", 8, 2),
177 GATE(HCLK_PERILP1, "cpll_hclk_perilp1_src", "cpll", 8, 1),
178 GATE(0, "gpll_hclk_perilp1_src", "gpll", 8, 0),
181 GATE(SCLK_SPI4, "clk_spi4", "clk_spi4_c", 9, 15),
182 GATE(SCLK_SPI2, "clk_spi2", "clk_spi2_c", 9, 14),
183 GATE(SCLK_SPI1, "clk_spi1", "clk_spi1_c", 9, 13),
184 GATE(SCLK_SPI0, "clk_spi0", "clk_spi0_c", 9, 12),
185 GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 9, 11),
186 GATE(SCLK_TSADC, "clk_tsadc", "clk_tsadc_c", 9, 10),
188 GATE(0, "clk_uart3_frac", "clk_uart3_frac_c", 9, 7),
189 GATE(0, "clk_uart3_div", "clk_uart3_div_c", 9, 6),
190 GATE(0, "clk_uart2_frac", "clk_uart2_frac_c", 9, 5),
191 GATE(0, "clk_uart2_div", "clk_uart2_div_c", 9, 4),
192 GATE(0, "clk_uart1_frac", "clk_uart1_frac_c", 9, 3),
193 GATE(0, "clk_uart1_div", "clk_uart1_div_c", 9, 2),
194 GATE(0, "clk_uart0_frac", "clk_uart0_frac_c", 9, 1),
195 GATE(0, "clk_uart0_div", "clk_uart0_div_c", 9, 0),
198 GATE(SCLK_VOP1_PWM, "clk_vop1_pwm", "clk_vop1_pwm_c", 10, 15),
199 GATE(SCLK_VOP0_PWM, "clk_vop0_pwm", "clk_vop0_pwm_c", 10, 14),
200 GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c", 10, 12),
201 GATE(DCLK_VOP1_DIV, "dclk_vop1_div", "dclk_vop1_div_c", 10, 13),
202 GATE(0, "hclk_vop1_pre", "hclk_vop1_pre_c", 10, 11),
203 GATE(ACLK_VOP1_PRE, "aclk_vop1_pre", "aclk_vop1_pre_c", 10, 10),
204 GATE(0, "hclk_vop0_pre", "hclk_vop0_pre_c", 10, 9),
205 GATE(ACLK_VOP0_PRE, "aclk_vop0_pre", "aclk_vop0_pre_c", 10, 8),
206 GATE(0, "clk_cifout_src", "clk_cifout_src_c", 10, 7),
207 GATE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", "clk_spdif_rec_dptx_c", 10, 6),
208 GATE(SCLK_I2C7, "clk_i2c7", "clk_i2c7_c", 10, 5),
209 GATE(SCLK_I2C3, "clk_i2c3", "clk_i2c3_c", 10, 4),
210 GATE(SCLK_I2C6, "clk_i2c6", "clk_i2c6_c", 10, 3),
211 GATE(SCLK_I2C2, "clk_i2c2", "clk_i2c2_c", 10, 2),
212 GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c", 10, 1),
213 GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c", 10, 0),
216 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15),
217 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14),
219 GATE(PCLK_EDP, "pclk_edp", "pclk_edp_c", 11, 11),
220 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_hdcp_c", 11, 10),
222 GATE(SCLK_DP_CORE, "clk_dp_core", "clk_dp_core_c", 11, 8),
223 GATE(SCLK_HDMI_CEC, "clk_hdmi_cec", "clk_hdmi_cec_c", 11, 7),
224 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6),
225 GATE(SCLK_ISP1, "clk_isp1", "clk_isp1_c", 11, 5),
226 GATE(SCLK_ISP0, "clk_isp0", "clk_isp0_c", 11, 4),
227 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_hdcp_c", 11, 3),
228 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_c", 11, 2),
229 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_c", 11, 1),
230 GATE(ACLK_VIO, "aclk_vio", "aclk_vio_c", 11, 0),
234 GATE(HCLK_SD, "hclk_sd", "hclk_sd_c", 12, 13),
235 GATE(ACLK_GIC_PRE, "aclk_gic_pre", "aclk_gic_pre_c", 12, 12),
236 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_c", 12, 11),
237 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_c", 12, 10),
238 GATE(HCLK_ISP0, "hclk_isp0", "hclk_isp0_c", 12, 9),
239 GATE(ACLK_ISP0, "aclk_isp0", "aclk_isp0_c", 12, 8),
241 GATE(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "clk_pciephy_ref100m_c", 12, 6),
243 GATE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_c", 12, 4),
244 GATE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_c", 12, 3),
245 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2),
246 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1),
247 GATE(ACLK_USB3, "aclk_usb3", "aclk_usb3_c", 12, 0),
250 GATE(SCLK_TESTCLKOUT2, "clk_testout2", "clk_testout2_c", 13, 15),
251 GATE(SCLK_TESTCLKOUT1, "clk_testout1", "clk_testout1_c", 13, 14),
252 GATE(SCLK_SPI5, "clk_spi5", "clk_spi5_c", 13, 13),
253 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 13, 12),
254 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 13, 12),
255 GATE(0, "clk_test", "clk_test_c", 13, 11),
257 GATE(0, "clk_test_frac", "clk_test_frac_c", 13, 9),
259 GATE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", "clk_uphy1_tcpdcore_c", 13, 7),
260 GATE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", "clk_uphy1_tcpdphy_ref_c", 13, 6),
261 GATE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", "clk_uphy0_tcpdcore_c", 13, 5),
262 GATE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", "clk_uphy0_tcpdphy_ref_c", 13, 4),
264 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 13, 1),
265 GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 13, 0),
269 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", 14, 13),
270 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", 14, 12),
271 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", 14, 11),
272 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", 14, 10),
273 GATE(0, "clk_dbg_pd_core_l", "armclkl", 14, 9),
275 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", 14, 6),
276 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", 14, 5),
277 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", 14, 4),
278 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", 14, 3),
279 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", 14, 2),
280 GATE(0, "clk_dbg_pd_core_b", "armclkb", 14, 1),
285 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", 15, 7),
286 GATE(0, "clk_dbg_noc", "clk_cs", 15, 6),
287 GATE(0, "clk_dbg_cxcs", "clk_cs", 15, 5),
288 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", 15, 4),
289 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", 15, 3),
290 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", 15, 2),
291 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", 15, 1),
292 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", 15, 0),
296 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", 16, 11),
297 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 16, 10),
298 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", 16, 9),
299 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 16, 8),
301 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", 16, 3),
302 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 16, 2),
303 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", 16, 1),
304 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 16, 0),
308 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", 17, 11),
309 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 17, 10),
310 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", 17, 9),
311 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 17, 8),
312 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", 17, 3),
313 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 17, 2),
314 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", 17, 1),
315 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 17, 0),
318 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", 18, 15),
319 GATE(0, "clk_ddr_mon_timer", "xin24m", 18, 14),
320 GATE(0, "clk_ddr_mon", "clk_ddrc_div2", 18, 13),
321 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 18, 12),
322 GATE(0, "clk_ddr_cic", "clk_ddrc_div2", 18, 11),
323 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", 18, 10),
324 GATE(0, "clk_ddrcfg_msch1", "clk_ddrc_div2", 18, 9),
325 GATE(0, "clk_ddrphy1", "clk_ddrc_div2", 18, 8),
326 GATE(0, "clk_ddrphy_ctrl1", "clk_ddrc_div2", 18, 7),
327 GATE(0, "clk_ddrc1", "clk_ddrc_div2", 18, 6),
328 GATE(0, "clk_ddr1_msch", "clk_ddrc_div2", 18, 5),
329 GATE(0, "clk_ddrcfg_msch0", "clk_ddrc_div2", 18, 4),
330 GATE(0, "clk_ddrphy0", "clk_ddrc_div2", 18, 3),
331 GATE(0, "clk_ddrphy_ctrl0", "clk_ddrc_div2", 18, 2),
332 GATE(0, "clk_ddrc0", "clk_ddrc_div2", 18, 1),
336 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", 19, 2),
337 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", 19, 1),
338 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", 19, 0),
341 GATE(0, "hclk_ahb1tom", "hclk_perihp", 20, 15),
342 GATE(0, "pclk_perihp_noc", "pclk_perihp", 20, 14),
343 GATE(0, "hclk_perihp_noc", "hclk_perihp", 20, 13),
344 GATE(0, "aclk_perihp_noc", "aclk_perihp", 20, 12),
345 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 20, 11),
346 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 20, 10),
347 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 20, 9),
348 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 20, 8),
349 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 20, 7),
350 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 20, 6),
351 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 20, 5),
352 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", 20, 4),
353 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 20, 2),
358 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", 21, 9),
359 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", 21, 8),
361 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", 21, 6),
362 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", 21, 5),
363 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", 21, 4),
364 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 21, 3),
365 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 21, 2),
366 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 21, 1),
367 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 21, 0),
370 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 22, 15),
371 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 22, 14),
372 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 22, 13),
373 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 22, 12),
374 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 22, 11),
375 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_perilp1", 22, 10),
376 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_perilp1", 22, 9),
377 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_perilp1", 22, 8),
378 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_perilp1", 22, 7),
379 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_perilp1", 22, 6),
380 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_perilp1", 22, 5),
381 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 22, 3),
382 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 22, 2),
383 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 22, 1),
384 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 22, 0),
388 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 23, 13),
389 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 23, 12),
390 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 23, 11),
391 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 23, 10),
392 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 23, 9),
393 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 23, 8),
394 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", 23, 7),
395 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", 23, 6),
396 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", 23, 5),
397 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", 23, 4),
398 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", 23, 3),
399 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", 23, 2),
400 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", 23, 1),
401 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", 23, 0),
404 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 24, 15),
405 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 24, 14),
406 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 24, 13),
407 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 24, 11),
408 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 24, 10),
409 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 24, 9),
410 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 24, 8),
412 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 24, 6),
413 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 24, 5),
414 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", 24, 4),
419 GATE(0, "hclk_sdio_noc", "hclk_perilp1", 25, 12),
420 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", 25, 11),
421 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 25, 10),
422 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", 25, 9),
423 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", 25, 8),
424 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 25, 7),
425 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 25, 6),
426 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 25, 5),
431 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 26, 11),
432 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 26, 10),
433 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 26, 9),
434 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 26, 8),
435 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 26, 7),
436 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 26, 6),
437 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 26, 5),
438 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 26, 4),
439 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 26, 3),
440 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 26, 2),
441 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 26, 1),
442 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 26, 0),
446 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 27, 8),
447 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 27, 7),
448 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 27, 6),
449 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 27, 5),
450 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 27, 4),
451 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", 27, 3),
452 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", 27, 2),
453 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", 27, 1),
454 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", 27, 0),
458 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 28, 7),
459 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 28, 6),
460 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", 28, 5),
461 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", 28, 4),
462 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 28, 3),
463 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 28, 2),
464 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", 28, 1),
465 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", 28, 0),
469 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", 29, 12),
470 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 29, 11),
471 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 29, 10),
472 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 29, 9),
473 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 29, 8),
474 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 29, 7),
475 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 29, 6),
476 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", 29, 5),
477 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", 29, 4),
478 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", 29, 3),
479 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 29, 2),
480 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 29, 1),
481 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", 29, 0),
485 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 30, 11),
486 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 30, 10),
488 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 30, 8),
490 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 30, 4),
491 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 30, 3),
492 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 30, 2),
493 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 30, 1),
494 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 30, 0),
498 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", 31, 10),
499 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", 31, 9),
500 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 31, 8),
501 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 31, 7),
502 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 31, 6),
503 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 31, 5),
504 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 31, 4),
505 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 31, 3),
506 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", 31, 2),
507 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", 31, 1),
512 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 32, 13),
513 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", 32, 12),
515 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 32, 10),
516 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 32, 9),
517 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 32, 8),
519 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 32, 4),
520 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", 32, 3),
521 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 32, 2),
522 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", 32, 1),
523 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 32, 0),
527 GATE(0, "hclk_sdmmc_noc", "hclk_sd", 33, 9),
528 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 33, 8),
529 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", 33, 5),
530 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", 33, 4),
531 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", 33, 3),
532 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", 33, 2),
533 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", 33, 1),
534 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", 33, 0),
538 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", 34, 6),
539 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 34, 5),
540 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 34, 4),
541 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 34, 3),
542 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 34, 2),
543 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 34, 1),
544 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 34, 0),