Lines Matching full:gate
253 GATE(0, "core_apll_clk", "apll", 0, 0),
254 GATE(0, "core_dpll_clk", "dpll", 0, 1),
255 GATE(0, "core_gpll_clk", "gpll", 0, 2),
262 GATE(SCLK_WIFI, "sclk_wifi", "sclk_wifi_c", 0, 10),
263 GATE(SCLK_RTC32K, "clk_rtc32k", "clk_rtc32k_c", 0, 11),
264 GATE(0, "core_npll_clk", "npll", 0, 12),
269 GATE(0, "clk_i2s0_div", "clk_i2s0_div_c", 1, 1),
270 GATE(0, "clk_i2s0_frac", "clk_i2s0_frac_f", 1, 2),
271 GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 1, 3),
272 GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 1, 4),
273 GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_f", 1, 5),
274 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 1, 6),
275 GATE(0, "clk_i2s1_out", "clk_i2s1_mux", 1, 7),
276 GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 1, 8),
277 GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_f", 1, 9),
278 GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", 1, 10),
279 GATE(0, "clk_i2s2_out", "clk_i2s2_mux", 1, 11),
280 GATE(0, "clk_spdif_div", "clk_spdif_div_c", 1, 12),
281 GATE(0, "clk_spdif_frac", "clk_spdif_frac_f", 1, 13),
282 GATE(0, "clk_uart0_div", "clk_uart0_div_c", 1, 14),
283 GATE(0, "clk_uart0_frac", "clk_uart0_frac_f", 1, 15),
286 GATE(0, "clk_uart1_div", "clk_uart1_div_c", 2, 0),
287 GATE(0, "clk_uart1_frac", "clk_uart1_frac_f", 2, 1),
288 GATE(0, "clk_uart2_div", "clk_uart2_div_c", 2, 2),
289 GATE(0, "clk_uart2_frac", "clk_uart2_frac_f", 2, 3),
290 GATE(SCLK_CRYPTO, "clk_crypto", "clk_crypto_c", 2, 4),
291 GATE(SCLK_TSP, "clk_tsp", "clk_tsp_c", 2, 5),
292 GATE(SCLK_TSADC, "clk_tsadc_src", "clk_tsadc_c", 2, 6),
293 GATE(SCLK_SPI, "clk_spi", "clk_spi_c", 2, 7),
294 GATE(SCLK_PWM, "clk_pwm", "clk_pwm_c", 2, 8),
295 GATE(SCLK_I2C0, "clk_i2c0_src", "clk_i2c0_c", 2, 9),
296 GATE(SCLK_I2C1, "clk_i2c1_src", "clk_i2c1_c", 2, 10),
297 GATE(SCLK_I2C2, "clk_i2c2_src", "clk_i2c2_c", 2, 11),
298 GATE(SCLK_I2C3, "clk_i2c3_src", "clk_i2c3_c", 2, 12),
299 GATE(SCLK_EFUSE, "clk_efuse", "clk_efuse_c", 2, 13),
300 GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 2, 14),
301 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_c", 2, 15),
304 GATE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", "clk_mac2phy_src_c", 3, 0),
305 GATE(SCLK_MAC2IO_SRC, "clk_mac2io_src", "clk_mac2io_src_c", 3, 1),
306 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_c", 3, 2),
309 GATE(SCLK_MAC2IO_OUT, "clk_mac2io_out", "clk_mac2io_out_c", 3, 5),
311 GATE(SCLK_OTP, "clk_otp", "clk_otp_c", 3, 8),
315 GATE(0, "periph_gclk_src", "gpll", 4, 0),
316 GATE(0, "periph_cclk_src", "cpll", 4, 1),
317 GATE(0, "hdmiphy_peri", "hdmiphy", 4, 2),
318 GATE(SCLK_SDMMC, "clk_mmc0_src", "clk_sdmmc_c", 4, 3),
319 GATE(SCLK_SDIO, "clk_sdio_src", "clk_sdio_c", 4, 4),
320 GATE(SCLK_EMMC, "clk_emmc_src", "clk_emmc_c", 4, 5),
321 GATE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", "clk_ref_usb3otg_src_c", 4, 6),
322 GATE(SCLK_USB3OTG_REF, "clk_usb3_otg0_ref", "xin24m", 4, 7),
323 GATE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", "clk_usb3otg_suspend_c", 4, 8),
325 GATE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", "clk_sdmmc_ext_c", 4, 10),
329 GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_c", 5, 0),
330 GATE(SCLK_RGA, "sclk_rga", "sclk_rga_c", 5, 0),
331 GATE(ACLK_VIO_PRE, "aclk_vio_pre", "aclk_vio_pre_c", 5, 2),
332 GATE(SCLK_CIF_OUT, "clk_cif_src", "clk_cif_src_c", 5, 3),
333 GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 5, 4),
334 GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 5, 5),
335 GATE(DCLK_LCDC_SRC, "vop_dclk_src", "vop_dclk_src_c", 5, 6),
339 GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_c", 6, 0),
340 GATE(SCLK_VDEC_CABAC, "sclk_cabac", "sclk_cabac_c", 6, 1),
341 GATE(SCLK_VDEC_CORE, "sclk_vdec_core", "sclk_vdec_core_c", 6, 2),
342 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_c", 6, 3),
343 GATE(SCLK_VENC_CORE, "sclk_venc", "sclk_venc_c", 6, 4),
344 GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 6, 5),
345 GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 6, 6),
346 GATE(SCLK_VENC_DSP, "sclk_venc_dsp", "sclk_venc_dsp_c", 6, 7),
358 GATE(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_pre_c", 8, 0),
359 GATE(HCLK_BUS_PRE, "hclk_bus_pre", "hclk_bus_pre_c", 8, 1),
360 GATE(PCLK_BUS_PRE, "pclk_bus_pre", "pclk_bus_pre_c", 8, 2),
361 GATE(0, "pclk_bus", "pclk_bus_pre", 8, 3),
362 GATE(0, "pclk_phy", "pclk_bus_pre", 8, 4),
363 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 8, 5),
364 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 8, 6),
365 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 8, 7),
366 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 8, 8),
367 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 8, 9),
368 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 8, 10),
372 GATE(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 9, 0),
373 GATE(SCLK_MAC2PHY_RXTX, "clk_gmac2phy_rx", "clk_mac2phy", 9, 1),
374 GATE(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy_out_c", 9, 2),
375 GATE(SCLK_MAC2PHY_REF, "clk_gmac2phy_ref", "clk_mac2phy", 9, 3),
376 GATE(SCLK_MAC2IO_RX, "clk_gmac2io_rx", "clk_mac2io", 9, 4),
377 GATE(SCLK_MAC2IO_TX, "clk_gmac2io_tx", "clk_mac2io", 9, 5),
378 GATE(SCLK_MAC2IO_REFOUT, "clk_gmac2io_refout", "clk_mac2io", 9, 6),
379 GATE(SCLK_MAC2IO_REF, "clk_gmac2io_ref", "clk_mac2io", 9, 7),
383 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 10, 0),
384 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_c", 10, 1),
385 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_c", 10, 2),
389 GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 11, 0),
391 GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 11, 4),
393 GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 11, 8),
405 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 14, 0),
406 GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 14, 1),
413 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 15, 3),
414 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 15, 4),
415 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 15, 5),
416 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 15, 6),
417 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 15, 7),
418 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 15, 8),
419 GATE(0, "pclk_efuse", "pclk_bus", 15, 9),
420 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 15, 10),
421 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 15, 11),
422 GATE(0, "aclk_bus_niu", "aclk_bus_pre", 15, 12),
423 GATE(0, "hclk_bus_niu", "hclk_bus_pre", 15, 13),
424 GATE(0, "pclk_bus_niu", "pclk_bus_pre", 15, 14),
425 GATE(0, "pclk_phy_niu", "pclk_phy", 15, 14),
429 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 16, 0),
430 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 16, 1),
431 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 16, 2),
432 GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 16, 3),
433 GATE(0, "pclk_stimer", "pclk_bus", 16, 4),
434 GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 16, 5),
435 GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 16, 6),
436 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 16, 7),
437 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 16, 8),
438 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 16, 9),
439 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 16, 10),
440 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 16, 11),
441 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 16, 12),
442 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 16, 13),
443 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 16, 14),
444 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 16, 15),
447 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", 17, 0),
449 GATE(PCLK_USB3_GRF, "pclk_usb3grf", "pclk_phy", 17, 2),
450 GATE(0, "pclk_ddrphy", "pclk_phy", 17, 3),
451 GATE(0, "pclk_cru", "pclk_bus", 17, 4),
452 GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy", 17, 5),
453 GATE(0, "pclk_sgrf", "pclk_bus", 17, 6),
454 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy", 17, 7),
455 GATE(0, "pclk_vdacphy", "pclk_bus", 17, 8),
457 GATE(0, "pclk_sim", "pclk_bus", 17, 10),
458 GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 17, 11),
459 GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 17, 12),
461 GATE(PCLK_USB2_GRF, "pclk_usb2grf", "pclk_phy", 17, 14),
462 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 17, 15),
476 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 19, 0),
477 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 19, 1),
478 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 19, 2),
480 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 19, 6),
481 GATE(HCLK_HOST0_ARB, "hclk_host0_arg", "hclk_peri", 19, 7),
482 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 19, 8),
483 GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 19, 9),
485 GATE(0, "aclk_peri_niu", "aclk_peri", 19, 11),
486 GATE(0, "hclk_peri_niu", "hclk_peri", 19, 12),
487 GATE(0, "pclk_peri_niu", "hclk_peri", 19, 13),
488 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 19, 14),
489 GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 19, 15),
496 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 21, 2),
497 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 21, 3),
498 GATE(0, "aclk_vop_niu", "aclk_vop_pre", 21, 4),
499 GATE(0, "hclk_vop_niu", "hclk_vio_pre", 21, 5),
500 GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 21, 6),
501 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 21, 7),
502 GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 21, 8),
503 GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 21, 9),
504 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 21, 10),
505 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 21, 11),
506 GATE(0, "hclk_ahb1tom", "hclk_vio_pre", 21, 12),
507 GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 21, 13),
508 GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 21, 14),
509 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 21, 15),
512 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 22, 0),
513 GATE(0, "hclk_vio_niu", "hclk_vio_pre", 22, 1),
514 GATE(0, "aclk_vio_niu", "aclk_vio_pre", 22, 2),
515 GATE(0, "aclk_rga_niu", "aclk_rga_pre", 22, 3),
516 GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 22, 4),
517 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 22, 5),
521 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 23, 0),
522 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 23, 1),
523 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 23, 2),
524 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 23, 3),
528 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 24, 0),
529 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 24, 1),
530 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 24, 2),
531 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 24, 3),
535 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 25, 0),
536 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 25, 1),
537 GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 25, 2),
538 GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 25, 3),
539 GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 25, 4),
540 GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 25, 5),
541 GATE(0, "aclk_axisram", "hclk_rkvenc", 25, 6),
545 GATE(ACLK_MAC2PHY, "aclk_gmac2phy", "aclk_gmac", 26, 0),
546 GATE(PCLK_MAC2PHY, "pclk_gmac2phy", "pclk_gmac", 26, 1),
547 GATE(ACLK_MAC2IO, "aclk_gmac2io", "aclk_gmac", 26, 2),
548 GATE(PCLK_MAC2IO, "pclk_gmac2io", "pclk_gmac", 26, 3),
549 GATE(0, "aclk_gmac_niu", "aclk_gmac", 26, 4),
550 GATE(0, "pclk_gmac_niu", "pclk_gmac", 26, 5),
558 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 28, 0),
559 GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy", 28, 1),
560 GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy", 28, 2),
561 GATE(0, "pclk_pmu", "pclk_bus", 28, 3),
562 GATE(0, "pclk_otp", "pclk_bus", 28, 4)