Home
last modified time | relevance | path

Searched +full:fpga +full:- +full:based (Results 1 – 25 of 59) sorted by relevance

123

/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dgef_ppc9a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
[all …]
H A Dgef_sbc310.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00010000>; // FPGA
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
[all …]
H A Dgef_sbc610.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
[all …]
H A Dge_imp3a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on: P2020 DS Device Tree Source
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmdio-mux-multiplexer.txt5 producer, gpio mux producer or generic register based mux producer.
9 - compatible : should be "mmio-mux-multiplexer"
10 - mux-controls : mux controller node to use for operating the mux
11 - mdio-parent-bus : phandle to the parent MDIO bus.
17 Documentation/devicetree/bindings/mux/mux-controller.txt
18 and Documentation/devicetree/bindings/net/mdio-mux.txt
24 fpga@66 { // fpga connected to i2c
25 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
26 "simple-mfd";
29 mux: mux-controller { // Mux Producer
[all …]
H A Dlitex,liteeth.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joel Stanley <joel@jms.id.au>
13 LiteETH is a small footprint and configurable Ethernet core for FPGA based
17 https://github.com/enjoy-digital/liteeth/.
20 - $ref: ethernet-controller.yaml#
28 - description: MAC registers
29 - description: MDIO registers
30 - description: Packet buffer
[all …]
/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dfpga-region.txt1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Region
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mux/
H A Dreg-mux.txt1 Generic register bitfield-based multiplexer controller bindings
7 - compatible : should be one of
8 "reg-mux" : if parent device of mux controller is not syscon device
9 "mmio-mux" : if parent device of mux controller is syscon device
10 - #mux-control-cells : <1>
11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
13 * Standard mux-controller bindings as decribed in mux-controller.txt
16 - idle-states : if present, the state the muxes will have when idle. The
21 pair in the mux-reg-masks array.
27 fpga@66 { // fpga connected to i2c
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 The CDX bus manages multiple FPGA based hardware devices, which
14 devices. These FPGA based devices can be added/modified dynamically
15 on run-time.
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
26 The msi-map property is used to associate the devices with the
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip FPGA {Q,}SPI Controllers
11 fabric IP cores they are based on
14 - Conor Dooley <conor.dooley@microchip.com>
19 - items:
20 - enum:
21 - microchip,mpfs-qspi
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_cyclone5_de10nano.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * based on socfpga_cyclone5_de0_nano_soc.dts
7 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Terasic DE10-Nano";
15 compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
28 fpga: bus@ff200000 { label
29 compatible = "simple-bus";
[all …]
/freebsd/share/man/man4/
H A Dsume.41 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
36 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
49 driver provides support for NetFPGA SUME Virtex-7 FPGA Development Board
51 The HDL design for the reference NIC project uses the RIFFA based DMA
72 .An -nosplit
87 Pre-built FPGA bitstream from the NetFPGA project may not work correctly.
92 Occasionally, the driver can get stuck in a non-IDLE TX state due to
/freebsd/sys/contrib/device-tree/Bindings/rng/
H A Dxiphera,xip8001b-trng.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rng/xiphera,xip8001b-trng.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xiphera XIP8001B-trng
10 - Atte Tommiska <atte.tommiska@xiphera.com>
13 Xiphera FPGA-based true random number generator intellectual property core.
17 const: xiphera,xip8001b-trng
23 - compatible
24 - reg
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dlitex,mmc.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Somlo <gsomlo@gmail.com>
13 LiteSDCard is a small footprint, configurable SDCard core for FPGA based
17 https://github.com/enjoy-digital/litesdcard/.
20 - $ref: mmc-controller.yaml#
28 - description: PHY registers
29 - description: CORE registers
30 - description: DMA Reader buffer
[all …]
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dxlnx,sd-fec.txt4 which provides high-throughput LDPC and Turbo Code implementations.
6 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
8 power and area savings versus implementations done in the FPGA fabric.
12 - compatible: Must be "xlnx,sd-fec-1.1"
13 - clock-names : List of input clock names from the following:
14 - "core_clk", Main processing clock for processing core (required)
15 - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
16 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
17 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
18 - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
[all …]
H A Dxlnx,sd-fec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cvetic, Dragan <dragan.cvetic@amd.com>
11 - Erim, Salih <salih.erim@amd.com>
15 which provides high-throughput LDPC and Turbo Code implementations.
17 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
19 power and area savings versus implementations done in the FPGA fabric.
23 const: xlnx,sd-fec-1.1
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dadi,axi-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI-DMAC DMA controller
10 FPGA-based DMA controller designed for use with high-speed converter hardware.
15 - Nuno Sa <nuno.sa@analog.com>
21 const: adi,axi-dmac-1.00.a
32 "#dma-cells":
39 This sub-node must contain a sub-node for each DMA channel. This node is
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dctu,ctucanfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CTU CAN FD Open-source IP Core
10 Open-source CAN FD IP core developed at the Czech Technical University in Prague
16 Integration in Xilinx Zynq SoC based system together with
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
21 …https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-…
24 - Pavel Pisa <pisa@cmp.felk.cvut.cz>
25 - Ondrej Ille <ondrej.ille@gmail.com>
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx51-ts4800.dts2 * Copyright 2015 Savoir-faire Linux
4 * This device tree is based on imx51-babbage.dts
9 /dts-v1/;
13 model = "Technologic Systems TS-4800";
14 compatible = "technologic,imx51-ts4800", "fsl,imx51";
17 stdout-path = &uart1;
27 clock-frequency = <22579200>;
31 clock-frequency = <24576000>;
35 backlight_reg: regulator-backlight {
36 compatible = "regulator-fixed";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,integrator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/dev/sfxge/common/
H A Defx_regs_mcdi_aoe.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2018 Solarflare Communications Inc. All rights reserved.
69 /* enum: Get FPGA Build registers */
79 /* enum: FPGA link information */
81 /* enum: Configure loopbacks and link on FPGA ports */
152 /* enum: PHY read connection from FC - may be not required */
154 /* enum: PHY read flags from FC - may be not required */
172 /* enum: MAC Set command - same as MC_CMD_SET_MAC */
184 /* enum: External FPGA port. */
[all …]
/freebsd/sys/dts/powerpc/
H A Dp3041ds.dts4 * Copyright 2010-2011 Freescale Semiconductor Inc.
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
67 bman-portals@ff4000000 {
68 bman-portal@0 {
69 cpu-handle = <&cpu0>;
71 bman-portal@4000 {
72 cpu-handle = <&cpu1>;
74 bman-portal@8000 {
[all …]
H A Dp5020ds.dts4 * Copyright 2010-2011 Freescale Semiconductor Inc.
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
67 bman-portals@ff4000000 {
68 bman-portal@0 {
69 cpu-handle = <&cpu0>;
71 bman-portal@4000 {
72 cpu-handle = <&cpu1>;
74 bman-portal@8000 {
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Debony.dts14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <0>; // Filled in by zImage
39 timebase-frequency = <0>; // Filled in by zImage
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/dac/
H A Dadi,ad3552r.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Nuno Sá <nuno.sa@analog.com>
16 https://www.analog.com/media/en/technical-documentation/data-sheets/ad3541r.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ad3542r.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/ad3551r.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/ad3552r.pdf
24 - adi,ad3541r
25 - adi,ad3542r
[all …]

123