xref: /freebsd/sys/contrib/device-tree/Bindings/dma/adi,axi-dmac.yaml (revision 2846c90520eb4cc74e24d586a0ea0f4a0006bc73) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Analog Devices AXI-DMAC DMA controller
8
9description: |
10  FPGA-based DMA controller designed for use with high-speed converter hardware.
11
12  http://analogdevicesinc.github.io/hdl/library/axi_dmac/index.html
13
14maintainers:
15  - Nuno Sa <nuno.sa@analog.com>
16
17additionalProperties: false
18
19properties:
20  compatible:
21    const: adi,axi-dmac-1.00.a
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  "#dma-cells":
33    const: 1
34
35  adi,channels:
36    deprecated: true
37    type: object
38    description:
39      This sub-node must contain a sub-node for each DMA channel. This node is
40      only required for IP versions older than 4.3.a and should otherwise be
41      omitted.
42    additionalProperties: false
43
44    properties:
45      "#size-cells":
46        const: 0
47      "#address-cells":
48        const: 1
49
50    patternProperties:
51      "^dma-channel@[0-9a-f]+$":
52        type: object
53        description:
54          DMA channel properties based on HDL compile-time configuration.
55        additionalProperties: false
56
57        properties:
58          reg:
59            maxItems: 1
60
61          adi,source-bus-width:
62            $ref: /schemas/types.yaml#/definitions/uint32
63            description: Width of the source bus in bits.
64            enum: [8, 16, 32, 64, 128]
65
66          adi,destination-bus-width:
67            $ref: /schemas/types.yaml#/definitions/uint32
68            description: Width of the destination bus in bits.
69            enum: [8, 16, 32, 64, 128]
70
71          adi,source-bus-type:
72            $ref: /schemas/types.yaml#/definitions/uint32
73            description: |
74              Type of the source bus.
75
76              0: Memory mapped AXI interface
77              1: Streaming AXI interface
78              2: FIFO interface
79            enum: [0, 1, 2]
80
81          adi,destination-bus-type:
82            $ref: /schemas/types.yaml#/definitions/uint32
83            description: Type of the destination bus (see adi,source-bus-type).
84            enum: [0, 1, 2]
85
86          adi,length-width:
87            deprecated: true
88            $ref: /schemas/types.yaml#/definitions/uint32
89            description: Width of the DMA transfer length register.
90
91          adi,cyclic:
92            deprecated: true
93            type: boolean
94            description:
95              Must be set if the channel supports hardware cyclic DMA transfers.
96
97          adi,2d:
98            deprecated: true
99            type: boolean
100            description:
101              Must be set if the channel supports hardware 2D DMA transfers.
102
103        required:
104          - reg
105          - adi,source-bus-width
106          - adi,destination-bus-width
107          - adi,source-bus-type
108          - adi,destination-bus-type
109
110    required:
111      - "#size-cells"
112      - "#address-cells"
113
114required:
115  - compatible
116  - reg
117  - interrupts
118  - clocks
119  - "#dma-cells"
120
121examples:
122  - |
123    dma-controller@7c420000 {
124        compatible = "adi,axi-dmac-1.00.a";
125        reg = <0x7c420000 0x10000>;
126        interrupts = <0 57 0>;
127        clocks = <&clkc 16>;
128        #dma-cells = <1>;
129    };
130