xref: /freebsd/sys/contrib/device-tree/Bindings/dma/adi,axi-dmac.yaml (revision 2846c90520eb4cc74e24d586a0ea0f4a0006bc73)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices AXI-DMAC DMA controller

description: |
  FPGA-based DMA controller designed for use with high-speed converter hardware.

  http://analogdevicesinc.github.io/hdl/library/axi_dmac/index.html

maintainers:
  - Nuno Sa <nuno.sa@analog.com>

additionalProperties: false

properties:
  compatible:
    const: adi,axi-dmac-1.00.a

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  "#dma-cells":
    const: 1

  adi,channels:
    deprecated: true
    type: object
    description:
      This sub-node must contain a sub-node for each DMA channel. This node is
      only required for IP versions older than 4.3.a and should otherwise be
      omitted.
    additionalProperties: false

    properties:
      "#size-cells":
        const: 0
      "#address-cells":
        const: 1

    patternProperties:
      "^dma-channel@[0-9a-f]+$":
        type: object
        description:
          DMA channel properties based on HDL compile-time configuration.
        additionalProperties: false

        properties:
          reg:
            maxItems: 1

          adi,source-bus-width:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: Width of the source bus in bits.
            enum: [8, 16, 32, 64, 128]

          adi,destination-bus-width:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: Width of the destination bus in bits.
            enum: [8, 16, 32, 64, 128]

          adi,source-bus-type:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: |
              Type of the source bus.

              0: Memory mapped AXI interface
              1: Streaming AXI interface
              2: FIFO interface
            enum: [0, 1, 2]

          adi,destination-bus-type:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: Type of the destination bus (see adi,source-bus-type).
            enum: [0, 1, 2]

          adi,length-width:
            deprecated: true
            $ref: /schemas/types.yaml#/definitions/uint32
            description: Width of the DMA transfer length register.

          adi,cyclic:
            deprecated: true
            type: boolean
            description:
              Must be set if the channel supports hardware cyclic DMA transfers.

          adi,2d:
            deprecated: true
            type: boolean
            description:
              Must be set if the channel supports hardware 2D DMA transfers.

        required:
          - reg
          - adi,source-bus-width
          - adi,destination-bus-width
          - adi,source-bus-type
          - adi,destination-bus-type

    required:
      - "#size-cells"
      - "#address-cells"

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - "#dma-cells"

examples:
  - |
    dma-controller@7c420000 {
        compatible = "adi,axi-dmac-1.00.a";
        reg = <0x7c420000 0x10000>;
        interrupts = <0 57 0>;
        clocks = <&clkc 16>;
        #dma-cells = <1>;
    };