xref: /freebsd/share/man/man4/sume.4 (revision fa9896e082a1046ff4fbc75fcba4d18d1f2efc19)
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27 .Dd August 30, 2020
28 .Dt SUME 4
29 .Os
30 .Sh NAME
31 .Nm sume
32 .Nd "NetFPGA SUME 4x10Gb Ethernet driver"
33 .Sh SYNOPSIS
34 To compile this driver into the kernel, place the following lines
35 in your kernel configuration file:
36 .Bd -ragged -offset indent
37 .Cd "device sume"
38 .Ed
39 .Pp
40 Alternatively, to load the driver as a module at boot time, place
41 the following line in
42 .Xr loader.conf 5 :
43 .Bd -literal -offset indent
44 if_sume_load="YES"
45 .Ed
46 .Sh DESCRIPTION
47 The
48 .Nm
49 driver provides support for NetFPGA SUME Virtex-7 FPGA Development Board
50 with the reference NIC bitstream loaded onto it.
51 The HDL design for the reference NIC project uses the RIFFA based DMA
52 engine to communicate with the host machine over PCIe.
53 Every packet is transmitted to / from the board via a single DMA
54 transaction, taking up to two or three interrupts per one transaction
55 which yields low performance.
56 .Pp
57 There is no support for Jumbo frames as the hardware is capable of
58 dealing only with frames with maximum size of 1514 bytes.
59 The hardware does not support multicast filtering, provides no checksums,
60 and offers no other offloading.
61 .Sh SEE ALSO
62 .Xr arp 4 ,
63 .Xr netgraph 4 ,
64 .Xr netintro 4 ,
65 .Xr ng_ether 4 ,
66 .Xr vlan 4 ,
67 .Xr ifconfig 8
68 .Sh AUTHORS
69 The Linux
70 .Nm
71 driver was originally written by
72 .An -nosplit
73 .An Bjoern A. Zeeb .
74 The
75 .Fx version and this manual page were written by
76 .An Denis Salopek
77 as a GSoC project.
78 More information about the project can be found here:
79 .Pa https://wiki.freebsd.org/SummerOfCode2020Projects/NetFPGA_SUME_Driver
80 .Sh BUGS
81 The reference NIC hardware design provides no mechanism for quiescing
82 inbound traffic from interfaces configured as DOWN.
83 All packets from administratively disabled interfaces are transferred to
84 main memory, leaving the driver with the task of dropping such packets,
85 thus consuming PCI bandwidth, interrupts and CPU cycles in vain.
86 .Pp
87 Pre-built FPGA bitstream from the NetFPGA project may not work correctly.
88 At higher RX packet rates, the newly incoming packets can overwrite the
89 ones in an internal FIFO so the packets would arrive in main memory
90 corrupted, until a physical reset of the board.
91 .Pp
92 Occasionally, the driver can get stuck in a non-IDLE TX state due to
93 a missed interrupt.
94 The driver includes a watchdog function which monitors for such a
95 condition and resets the board automatically.
96 For more details, visit the NetFPGA SUME project site.
97