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/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pic.c23 * -----------------
26 * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27 * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
33 * -----
61 * -------------------
62 * For actually manipulating IRQs (masking, enabling, clearing, etc) this
65 * for external interrupts. The irq_chip structures provide the hooks needed
71 * you'll also notice that there is an irq_chip defined for external
72 * interrupts even though there is no external interrupt group. The reason
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STi System Configuration Controlled IRQs
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 On STi based systems; External, CTI (Core Sight), PMU (Performance
14 Management), and PL310 L2 Cache IRQs are controlled using System
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
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H A Dmicrochip,pic32-evic.txt5 It handles all internal and external interrupts. This controller exists outside
9 External interrupts have a software configurable edge polarity. Non external
14 -------------------
16 - compatible: Should be "microchip,pic32mzda-evic"
17 - reg: Specifies physical base address and size of register range.
18 - interrupt-controller: Identifies the node as an interrupt controller.
19 - #interrupt cells: Specifies the number of cells used to encode an interrupt
25 hw_irq - represents the hardware interrupt number as in the data sheet.
26 irq_type - is used to describe the type and polarity of an interrupt. For
28 IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
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H A Dti,pruss-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
17 various other PRUSS internal and external peripherals. The first 2 output
19 remaining 8 (2 through 9) connected to external interrupt controllers
22 The property "ti,irqs-reserved" is used for denoting the connection
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H A Dmicrochip,sama7g5-eic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip External Interrupt Controller
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
14 support for handling up to 2 external interrupt lines.
19 - microchip,sama7g5-eic
24 interrupt-controller: true
26 '#interrupt-cells':
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H A Dactions,owl-sirq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
15 and S900) and provides support for handling up to 3 external interrupt lines.
20 - actions,s500-sirq
21 - actions,s700-sirq
22 - actions,s900-sirq
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H A Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
4 for dynamic IRQ routing, load balancing of common/external IRQs towards core
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
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/linux/arch/mips/lantiq/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* register definitions - internal irqs */
32 /* register definitions - external irqs */
38 /* number of external interrupts */
45 * irqs generated by devices attached to the EBU need to be acked in
59 /* we have a cascade of 8 irqs */
75 return -1; in ltq_eiu_get_irq()
80 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_disable_irq()
98 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_mask_and_ack_irq()
117 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_ack_irq()
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/linux/arch/arc/kernel/
H A Dintc-compact.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
18 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
19 * -Called very early (start_kernel -> setup_arch -> setup_processor)
22 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
32 * Write to register, even if no LV2 IRQs configured to reset it in arc_init_IRQ()
38 pr_info("Level-2 interrupts bitset %x\n", level_mask); in arc_init_IRQ()
41 * Disable all IRQ lines so faulty external hardware won't in arc_init_IRQ()
54 * ARC700 core includes a simple on-chip intc supporting
55 * -per IRQ enable/disable
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H A Dintc-arcv2.c1 // SPDX-License-Identifier: GPL-2.0-only
17 unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8; member
19 unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
25 * -Called very early (start_kernel -> setup_arch -> setup_processor)
26 * -Platform Independent (must for any ARC Core)
27 * -Needed for each CPU (hence not foldable into init_IRQ)
60 * Typical builds though have only two levels (0-high, 1-low) in arc_init_IRQ()
61 * Linux by default uses lower prio 1 for most irqs, reserving 0 for in arc_init_IRQ()
67 irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ in arc_init_IRQ()
68 pr_info("archs-intc\t: %d priority levels (default %d)%s\n", in arc_init_IRQ()
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/linux/drivers/irqchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
181 will be called irq-lan966x-oic.
222 bool "J-Core integrated AIC" if COMPILE_TEST
226 Support for the J-Core integrated AIC.
233 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
236 Enable support for the Renesas Interrupt Controller for external
237 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
240 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
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H A Dirq-mchp-eic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Microchip External Interrupt Controller driver
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
28 * struct mchp_eic - EIC private data structure
32 * @irqs: irqs b/w eic and gic
33 * @scfg: backup for scfg registers (necessary for backup and self-refresh mode)
40 u32 irqs[MCHP_EIC_NIRQ]; member
51 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
53 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
62 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
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H A Dirq-pic32-evic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/mach-pic32/pic32.h>
53 return (struct evic_chip_data *)data->domain->host_data; in irqd_to_priv()
59 * External interrupts can be either edge rising or edge falling, in pic32_set_ext_polarity()
70 return -EINVAL; in pic32_set_ext_polarity()
84 return -EBADR; in pic32_set_type_edge()
86 /* set polarity for external interrupts only */ in pic32_set_type_edge()
87 for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) { in pic32_set_type_edge()
88 if (priv->ext_irqs[i] == data->hwirq) { in pic32_set_type_edge()
127 struct evic_chip_data *priv = d->host_data; in pic32_irq_domain_map()
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H A Dirq-renesas-intc-irqpin.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas INTC External IRQ Pin Driver
33 /* INTC external IRQ PIN hardware register access:
35 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
36 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
37 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
38 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
41 * (*) May be accessed by more than one driver instance - lock needed
42 * (**) Read-modify-write access by one driver instance - lock needed
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/linux/include/soc/at91/
H A Datmel_tcb.h17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
22 * These TC blocks may have up to nine external pins: TCLK0..2 signals for
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
50 * struct atmel_tc - information about a Timer/Counter Block
60 * On some platforms, each TC channel has its own clocks and IRQs,
64 * Likewise, drivers should request irqs independently for each
80 /* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
85 * Two registers have block-wide controls. These are: configuring the three
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/linux/drivers/extcon/
H A Dextcon-intel-cht-wc.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
10 #include <linux/extcon-provider.h>
24 #include "extcon-intel.h"
67 /* 0 - open drain, 1 - regular push-pull output */
69 /* 0 - pin is controlled by SW, 1 - by HW */
125 * According to the spec. we should read the USB-ID pin ADC value here in cht_wc_extcon_get_id()
126 * to determine the resistance of the used pull-down resister and then in cht_wc_extcon_get_id()
129 * a combination of a charging port with one or more USB-A ports, so in cht_wc_extcon_get_id()
131 * is hard to read / badly-worded so some of them actually indicate in cht_wc_extcon_get_id()
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/linux/arch/powerpc/sysdev/
H A Dipic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* External IRQS */
32 /* System External Interrupt Mask Register */
52 bit mask = 1 << (31 - bit) */
/linux/arch/s390/include/asm/
H A Dirq.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 /* External interruption codes */
75 unsigned int irqs[NR_ARCH_IRQS]; member
82 __this_cpu_inc(irq_stat.irqs[irq]); in inc_irq_stat()
/linux/drivers/mfd/
H A Dmax77714.c1 // SPDX-License-Identifier: GPL-2.0-only
18 { .name = "max77714-watchdog" },
19 { .name = "max77714-rtc" },
63 .name = "max77714-pmic",
67 .irqs = max77714_top_irqs,
73 * the external oscillator by setting the XOSC_RETRY bit. If the external
88 return dev_err_probe(dev, err, "Failed to configure the external oscillator\n"); in max77714_setup_xosc()
92 return dev_err_probe(dev, err, "Failed to read external oscillator status\n"); in max77714_setup_xosc()
98 status & MAX77714_32K_STATUS_32KSOURCE ? "internal" : "external", in max77714_setup_xosc()
106 struct device *dev = &client->dev; in max77714_probe()
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/linux/arch/arm/mach-s3c/
H A Dirqs-s3c64xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
9 * S3C64XX - IRQ support
15 /* we keep the first set of CPU IRQs out of the range of
31 /* VIC based IRQs */
123 #define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
125 /* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
160 /* Some boards have their own IRQs behind this */
/linux/arch/arm/mach-pxa/
H A Dpxa27x.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include "addr-map.h"
7 #include "pxa2xx-regs.h"
8 #include "mfp-pxa27x.h"
9 #include "irqs.h"
15 #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
/linux/drivers/gpu/drm/mcde/
H A Dmcde_display.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 #include <linux/dma-buf.h>
11 #include <linux/media-bus-format.h>
79 /* Handle display IRQs */ in mcde_display_irq()
80 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
81 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
82 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
85 * Handle IRQs from the DSI link. All IRQs from the DSI links in mcde_display_irq()
92 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
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/linux/arch/sh/boards/mach-x3proto/
H A Dilsel.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/boards/mach-x3proto/ilsel.c
5 * Helper routines for SH-X3 proto board ILSEL.
7 * Copyright (C) 2007 - 2010 Paul Mundt
21 * ILSEL0 - 0xb8100004 [ Levels 1 - 4 ]
22 * ILSEL1 - 0xb8100006 [ Levels 5 - 8 ]
23 * ILSEL2 - 0xb8100008 [ Levels 9 - 12 ]
24 * ILSEL3 - 0xb810000a [ Levels 13 - 15 ]
34 * Supported levels are 1 - 15 spread across ILSEL0 - ILSEL4, mapping
35 * directly to IRLs. As the IRQs are numbered in reverse order relative
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/linux/arch/sh/boards/
H A Dboard-polaris.c1 // SPDX-License-Identifier: GPL-2.0
5 * Polaris-specific resource declaration
21 #include <mach-se/mach/se.h>
36 .name = "smsc911x-memory",
42 .name = "smsc911x-irq",
81 .id = -1,
98 printk(KERN_INFO "Configuring Polaris external bus\n"); in polaris_initialise()
108 /* Configure area 5 for 32-bit access */ in polaris_initialise()
119 /* External IRQs */
135 .name = "sh7709-ext",
/linux/drivers/pcmcia/
H A Ddb1xxx_ss.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * The Db1000 is used as a reference: Per-socket card-, carddetect- and
14 * statuschange IRQs connected to SoC GPIOs, control and status register
15 * bits arranged in per-socket groups in an external PLD. All boards
19 * - Pb1100/Pb1500: single socket only; voltage key bits VS are
21 * - Au1200-based: additional card-eject irqs, irqs not gpios!
22 * - Db1300: Db1200-like, no pwr ctrl, single socket (#1).
37 #include <asm/mach-au1x00/au1000.h>
38 #include <asm/mach-db1x00/bcsr.h>
57 int stschg_irq; /* card-status-change irq */
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