1*93da9991SClaudiu Beznea# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*93da9991SClaudiu Beznea%YAML 1.2 3*93da9991SClaudiu Beznea--- 4*93da9991SClaudiu Beznea$id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml# 5*93da9991SClaudiu Beznea$schema: http://devicetree.org/meta-schemas/core.yaml# 6*93da9991SClaudiu Beznea 7*93da9991SClaudiu Bezneatitle: Microchip External Interrupt Controller 8*93da9991SClaudiu Beznea 9*93da9991SClaudiu Bezneamaintainers: 10*93da9991SClaudiu Beznea - Claudiu Beznea <claudiu.beznea@microchip.com> 11*93da9991SClaudiu Beznea 12*93da9991SClaudiu Bezneadescription: 13*93da9991SClaudiu Beznea This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides 14*93da9991SClaudiu Beznea support for handling up to 2 external interrupt lines. 15*93da9991SClaudiu Beznea 16*93da9991SClaudiu Bezneaproperties: 17*93da9991SClaudiu Beznea compatible: 18*93da9991SClaudiu Beznea enum: 19*93da9991SClaudiu Beznea - microchip,sama7g5-eic 20*93da9991SClaudiu Beznea 21*93da9991SClaudiu Beznea reg: 22*93da9991SClaudiu Beznea maxItems: 1 23*93da9991SClaudiu Beznea 24*93da9991SClaudiu Beznea interrupt-controller: true 25*93da9991SClaudiu Beznea 26*93da9991SClaudiu Beznea '#interrupt-cells': 27*93da9991SClaudiu Beznea const: 2 28*93da9991SClaudiu Beznea description: 29*93da9991SClaudiu Beznea The first cell is the input IRQ number (between 0 and 1), the second cell 30*93da9991SClaudiu Beznea is the trigger type as defined in interrupt.txt present in this directory. 31*93da9991SClaudiu Beznea 32*93da9991SClaudiu Beznea interrupts: 33*93da9991SClaudiu Beznea description: | 34*93da9991SClaudiu Beznea Contains the GIC SPI IRQs mapped to the external interrupt lines. They 35*93da9991SClaudiu Beznea should be specified sequentially from output 0 to output 1. 36*93da9991SClaudiu Beznea minItems: 2 37*93da9991SClaudiu Beznea maxItems: 2 38*93da9991SClaudiu Beznea 39*93da9991SClaudiu Beznea clocks: 40*93da9991SClaudiu Beznea maxItems: 1 41*93da9991SClaudiu Beznea 42*93da9991SClaudiu Beznea clock-names: 43*93da9991SClaudiu Beznea const: pclk 44*93da9991SClaudiu Beznea 45*93da9991SClaudiu Beznearequired: 46*93da9991SClaudiu Beznea - compatible 47*93da9991SClaudiu Beznea - reg 48*93da9991SClaudiu Beznea - interrupt-controller 49*93da9991SClaudiu Beznea - '#interrupt-cells' 50*93da9991SClaudiu Beznea - interrupts 51*93da9991SClaudiu Beznea - clocks 52*93da9991SClaudiu Beznea - clock-names 53*93da9991SClaudiu Beznea 54*93da9991SClaudiu BezneaadditionalProperties: false 55*93da9991SClaudiu Beznea 56*93da9991SClaudiu Bezneaexamples: 57*93da9991SClaudiu Beznea - | 58*93da9991SClaudiu Beznea #include <dt-bindings/clock/at91.h> 59*93da9991SClaudiu Beznea #include <dt-bindings/interrupt-controller/arm-gic.h> 60*93da9991SClaudiu Beznea 61*93da9991SClaudiu Beznea eic: interrupt-controller@e1628000 { 62*93da9991SClaudiu Beznea compatible = "microchip,sama7g5-eic"; 63*93da9991SClaudiu Beznea reg = <0xe1628000 0x100>; 64*93da9991SClaudiu Beznea interrupt-parent = <&gic>; 65*93da9991SClaudiu Beznea interrupt-controller; 66*93da9991SClaudiu Beznea #interrupt-cells = <2>; 67*93da9991SClaudiu Beznea interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 68*93da9991SClaudiu Beznea <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 69*93da9991SClaudiu Beznea clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 70*93da9991SClaudiu Beznea clock-names = "pclk"; 71*93da9991SClaudiu Beznea }; 72*93da9991SClaudiu Beznea 73*93da9991SClaudiu Beznea... 74