1*c78a41fcSArnd Bergmann /* SPDX-License-Identifier: GPL-2.0 */ 2*c78a41fcSArnd Bergmann /* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h 3*c78a41fcSArnd Bergmann * 4*c78a41fcSArnd Bergmann * Copyright 2008 Openmoko, Inc. 5*c78a41fcSArnd Bergmann * Copyright 2008 Simtec Electronics 6*c78a41fcSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 7*c78a41fcSArnd Bergmann * http://armlinux.simtec.co.uk/ 8*c78a41fcSArnd Bergmann * 9*c78a41fcSArnd Bergmann * S3C64XX - IRQ support 10*c78a41fcSArnd Bergmann */ 11*c78a41fcSArnd Bergmann 12*c78a41fcSArnd Bergmann #ifndef __ASM_MACH_S3C64XX_IRQS_H 13*c78a41fcSArnd Bergmann #define __ASM_MACH_S3C64XX_IRQS_H __FILE__ 14*c78a41fcSArnd Bergmann 15*c78a41fcSArnd Bergmann /* we keep the first set of CPU IRQs out of the range of 16*c78a41fcSArnd Bergmann * the ISA space, so that the PC104 has them to itself 17*c78a41fcSArnd Bergmann * and we don't end up having to do horrible things to the 18*c78a41fcSArnd Bergmann * standard ISA drivers.... 19*c78a41fcSArnd Bergmann * 20*c78a41fcSArnd Bergmann * note, since we're using the VICs, our start must be a 21*c78a41fcSArnd Bergmann * mulitple of 32 to allow the common code to work 22*c78a41fcSArnd Bergmann */ 23*c78a41fcSArnd Bergmann 24*c78a41fcSArnd Bergmann #define S3C_IRQ_OFFSET (32) 25*c78a41fcSArnd Bergmann 26*c78a41fcSArnd Bergmann #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) 27*c78a41fcSArnd Bergmann 28*c78a41fcSArnd Bergmann #define IRQ_VIC0_BASE S3C_IRQ(0) 29*c78a41fcSArnd Bergmann #define IRQ_VIC1_BASE S3C_IRQ(32) 30*c78a41fcSArnd Bergmann 31*c78a41fcSArnd Bergmann /* VIC based IRQs */ 32*c78a41fcSArnd Bergmann 33*c78a41fcSArnd Bergmann #define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) 34*c78a41fcSArnd Bergmann #define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) 35*c78a41fcSArnd Bergmann 36*c78a41fcSArnd Bergmann /* VIC0 */ 37*c78a41fcSArnd Bergmann 38*c78a41fcSArnd Bergmann #define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) 39*c78a41fcSArnd Bergmann #define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) 40*c78a41fcSArnd Bergmann #define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) 41*c78a41fcSArnd Bergmann #define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) 42*c78a41fcSArnd Bergmann #define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) 43*c78a41fcSArnd Bergmann #define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) 44*c78a41fcSArnd Bergmann #define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) 45*c78a41fcSArnd Bergmann #define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) 46*c78a41fcSArnd Bergmann #define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) 47*c78a41fcSArnd Bergmann #define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) 48*c78a41fcSArnd Bergmann #define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) 49*c78a41fcSArnd Bergmann #define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) 50*c78a41fcSArnd Bergmann #define IRQ_POST0 S3C64XX_IRQ_VIC0(9) 51*c78a41fcSArnd Bergmann #define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) 52*c78a41fcSArnd Bergmann #define IRQ_2D S3C64XX_IRQ_VIC0(11) 53*c78a41fcSArnd Bergmann #define IRQ_TVENC S3C64XX_IRQ_VIC0(12) 54*c78a41fcSArnd Bergmann #define IRQ_SCALER S3C64XX_IRQ_VIC0(13) 55*c78a41fcSArnd Bergmann #define IRQ_BATF S3C64XX_IRQ_VIC0(14) 56*c78a41fcSArnd Bergmann #define IRQ_JPEG S3C64XX_IRQ_VIC0(15) 57*c78a41fcSArnd Bergmann #define IRQ_MFC S3C64XX_IRQ_VIC0(16) 58*c78a41fcSArnd Bergmann #define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) 59*c78a41fcSArnd Bergmann #define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) 60*c78a41fcSArnd Bergmann #define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) 61*c78a41fcSArnd Bergmann #define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) 62*c78a41fcSArnd Bergmann #define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) 63*c78a41fcSArnd Bergmann #define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) 64*c78a41fcSArnd Bergmann #define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) 65*c78a41fcSArnd Bergmann #define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) 66*c78a41fcSArnd Bergmann #define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) 67*c78a41fcSArnd Bergmann #define IRQ_WDT S3C64XX_IRQ_VIC0(26) 68*c78a41fcSArnd Bergmann #define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) 69*c78a41fcSArnd Bergmann #define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) 70*c78a41fcSArnd Bergmann #define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) 71*c78a41fcSArnd Bergmann #define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) 72*c78a41fcSArnd Bergmann #define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) 73*c78a41fcSArnd Bergmann 74*c78a41fcSArnd Bergmann /* VIC1 */ 75*c78a41fcSArnd Bergmann 76*c78a41fcSArnd Bergmann #define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) 77*c78a41fcSArnd Bergmann #define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) 78*c78a41fcSArnd Bergmann #define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) 79*c78a41fcSArnd Bergmann #define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) 80*c78a41fcSArnd Bergmann #define IRQ_AC97 S3C64XX_IRQ_VIC1(4) 81*c78a41fcSArnd Bergmann #define IRQ_UART0 S3C64XX_IRQ_VIC1(5) 82*c78a41fcSArnd Bergmann #define IRQ_UART1 S3C64XX_IRQ_VIC1(6) 83*c78a41fcSArnd Bergmann #define IRQ_UART2 S3C64XX_IRQ_VIC1(7) 84*c78a41fcSArnd Bergmann #define IRQ_UART3 S3C64XX_IRQ_VIC1(8) 85*c78a41fcSArnd Bergmann #define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) 86*c78a41fcSArnd Bergmann #define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) 87*c78a41fcSArnd Bergmann #define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) 88*c78a41fcSArnd Bergmann #define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) 89*c78a41fcSArnd Bergmann #define IRQ_NFC S3C64XX_IRQ_VIC1(13) 90*c78a41fcSArnd Bergmann #define IRQ_CFCON S3C64XX_IRQ_VIC1(14) 91*c78a41fcSArnd Bergmann #define IRQ_USBH S3C64XX_IRQ_VIC1(15) 92*c78a41fcSArnd Bergmann #define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) 93*c78a41fcSArnd Bergmann #define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) 94*c78a41fcSArnd Bergmann #define IRQ_IIC S3C64XX_IRQ_VIC1(18) 95*c78a41fcSArnd Bergmann #define IRQ_HSItx S3C64XX_IRQ_VIC1(19) 96*c78a41fcSArnd Bergmann #define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) 97*c78a41fcSArnd Bergmann #define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) 98*c78a41fcSArnd Bergmann #define IRQ_MSM S3C64XX_IRQ_VIC1(22) 99*c78a41fcSArnd Bergmann #define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) 100*c78a41fcSArnd Bergmann #define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) 101*c78a41fcSArnd Bergmann #define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) 102*c78a41fcSArnd Bergmann #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ 103*c78a41fcSArnd Bergmann #define IRQ_OTG S3C64XX_IRQ_VIC1(26) 104*c78a41fcSArnd Bergmann #define IRQ_IRDA S3C64XX_IRQ_VIC1(27) 105*c78a41fcSArnd Bergmann #define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) 106*c78a41fcSArnd Bergmann #define IRQ_SEC S3C64XX_IRQ_VIC1(29) 107*c78a41fcSArnd Bergmann #define IRQ_PENDN S3C64XX_IRQ_VIC1(30) 108*c78a41fcSArnd Bergmann #define IRQ_TC IRQ_PENDN 109*c78a41fcSArnd Bergmann #define IRQ_ADC S3C64XX_IRQ_VIC1(31) 110*c78a41fcSArnd Bergmann 111*c78a41fcSArnd Bergmann /* compatibility for device defines */ 112*c78a41fcSArnd Bergmann 113*c78a41fcSArnd Bergmann #define IRQ_IIC1 IRQ_S3C6410_IIC1 114*c78a41fcSArnd Bergmann 115*c78a41fcSArnd Bergmann /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series 116*c78a41fcSArnd Bergmann * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE 117*c78a41fcSArnd Bergmann * which we place after the pair of VICs. */ 118*c78a41fcSArnd Bergmann 119*c78a41fcSArnd Bergmann #define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) 120*c78a41fcSArnd Bergmann 121*c78a41fcSArnd Bergmann #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) 122*c78a41fcSArnd Bergmann #define IRQ_EINT(x) S3C_EINT(x) 123*c78a41fcSArnd Bergmann #define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) 124*c78a41fcSArnd Bergmann 125*c78a41fcSArnd Bergmann /* Next the external interrupt groups. These are similar to the IRQ_EINT(x) 126*c78a41fcSArnd Bergmann * that they are sourced from the GPIO pins but with a different scheme for 127*c78a41fcSArnd Bergmann * priority and source indication. 128*c78a41fcSArnd Bergmann * 129*c78a41fcSArnd Bergmann * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO 130*c78a41fcSArnd Bergmann * interrupts, but for historical reasons they are kept apart from these 131*c78a41fcSArnd Bergmann * next interrupts. 132*c78a41fcSArnd Bergmann * 133*c78a41fcSArnd Bergmann * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the 134*c78a41fcSArnd Bergmann * machine specific support files. 135*c78a41fcSArnd Bergmann */ 136*c78a41fcSArnd Bergmann 137*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP1_NR (15) 138*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP2_NR (8) 139*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP3_NR (5) 140*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP4_NR (14) 141*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP5_NR (7) 142*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP6_NR (10) 143*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP7_NR (16) 144*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP8_NR (15) 145*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP9_NR (9) 146*c78a41fcSArnd Bergmann 147*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP_BASE S3C_EINT(28) 148*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) 149*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) 150*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) 151*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) 152*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) 153*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) 154*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) 155*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) 156*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) 157*c78a41fcSArnd Bergmann 158*c78a41fcSArnd Bergmann #define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) 159*c78a41fcSArnd Bergmann 160*c78a41fcSArnd Bergmann /* Some boards have their own IRQs behind this */ 161*c78a41fcSArnd Bergmann #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) 162*c78a41fcSArnd Bergmann 163*c78a41fcSArnd Bergmann /* Set the default nr_irqs, boards can override if necessary */ 164*c78a41fcSArnd Bergmann #define S3C64XX_NR_IRQS IRQ_BOARD_START 165*c78a41fcSArnd Bergmann 166*c78a41fcSArnd Bergmann /* Compatibility */ 167*c78a41fcSArnd Bergmann 168*c78a41fcSArnd Bergmann #define IRQ_ONENAND IRQ_ONENAND0 169*c78a41fcSArnd Bergmann #define IRQ_I2S0 IRQ_S3C6410_IIS 170*c78a41fcSArnd Bergmann 171*c78a41fcSArnd Bergmann #endif /* __ASM_MACH_S3C64XX_IRQS_H */ 172*c78a41fcSArnd Bergmann 173