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/linux/arch/mips/bcm63xx/
H A Dclk.c33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
43 static void bcm_hwclock_set(u32 mask, int enable) in bcm_hwclock_set() argument
48 if (enable) in bcm_hwclock_set()
49 reg |= mask; in bcm_hwclock_set()
51 reg &= ~mask; in bcm_hwclock_set()
58 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
60 u32 mask; in enet_misc_set() local
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/linux/include/linux/iio/common/
H A Dst_sensors.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright 2012-2013 STMicroelectronics Inc.
53 #define ST_SENSORS_LSM_CHANNELS_EXT(device_type, mask, index, mod, \ argument
58 .info_mask_separate = mask, \
66 .shift = sbits - rbits, \
73 #define ST_SENSORS_LSM_CHANNELS(device_type, mask, index, mod, \ argument
75 ST_SENSORS_LSM_CHANNELS_EXT(device_type, mask, index, mod, \
93 u8 mask; member
99 u8 mask; member
106 u8 mask; member
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/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
49 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
56 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
62 #define SSCR0_RIM BIT(22) /* Receive FIFO overrun interrupt mask */
63 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
64 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
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H A Dvia-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
99 void viafb_irq_enable(u32 mask);
100 void viafb_irq_disable(u32 mask);
117 #define VDE_I_HQV1EN 0x00000800 /* Second HQV engine enable */
122 #define VDE_I_DVISNSEN 0x00010000 /* DVI sense enable */
123 #define VDE_I_VSYNC2EN 0x00020000 /* Sec Disp VSYNC enable */
124 #define VDE_I_MCCFIEN 0x00040000 /* MC comp frame int mask enable */
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/linux/drivers/net/wireless/ath/ath5k/
H A Dreg.h2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dmax6697.txt4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
24 Only valid for MAX6581. Set to enable extended temperature range.
26 - beta-compensation-enable
27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
34 - over-temperature-mask
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/linux/drivers/media/rc/
H A Dite-cir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
40 /* enable rx */
53 /* enable tx FIFO space available interrupt */
98 /* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
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H A Drc-loopback.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Loopback driver for rc-core,
8 * which is useful for (scripted) debugging of rc-core without
16 #include <media/rc-core.h>
18 #define DRIVER_NAME "rc-loopback"
36 static int loop_set_tx_mask(struct rc_dev *dev, u32 mask) in loop_set_tx_mask() argument
38 struct loopback_dev *lodev = dev->priv; in loop_set_tx_mask()
40 if ((mask & (RXMASK_NARROWBAND | RXMASK_WIDEBAND)) != mask) { in loop_set_tx_mask()
41 dev_dbg(&dev->dev, "invalid tx mask: %u\n", mask); in loop_set_tx_mask()
45 dev_dbg(&dev->dev, "setting tx mask: %u\n", mask); in loop_set_tx_mask()
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/linux/drivers/media/platform/ti/davinci/
H A Dvpif.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
139 /* Macro for Generating mask */
145 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
168 /* Mask various length */
183 /* bit position of clock and channel enable in vpif_chn_ctrl register */
262 /* inline function to enable/disable channel0 */
263 static inline void enable_channel0(int enable) in enable_channel0() argument
265 if (enable) in enable_channel0()
271 /* inline function to enable/disable channel1 */
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dpoplar-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/pinctrl/hisi.h>
10 /* value, enable bits, disable bits, mask */
11 #define PINCTRL_PULLDOWN(value, enable, disable, mask) \ argument
12 (value << 13) (enable << 13) (disable << 13) (mask << 13)
13 #define PINCTRL_PULLUP(value, enable, disable, mask) \ argument
14 (value << 12) (enable << 12) (disable << 12) (mask << 12)
15 #define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) argument
16 #define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) argument
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/linux/drivers/usb/serial/
H A Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
22 // above are used internally to indicate that we must enable access
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
32 #define IER 1 // ! Interrupt Enable Register
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
57 #define IER_RX 0x01 // Enable receive interrupt
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/linux/include/uapi/linux/
H A Dserial_reg.h1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
24 #define UART_IER 1 /* Out: Interrupt Enable Register */
25 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
26 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
28 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
32 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
36 #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */
55 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
83 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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/linux/drivers/firmware/imx/
H A Dimx-scu-irq.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/firmware/imx/rsrc.h>
40 u32 mask; member
43 u8 enable; member
47 u32 mask; member
91 if (scu_irq_wakeup[i].mask) { in imx_scu_irq_work_handler()
105 if (scu_irq_wakeup[i].mask & irq_status) { in imx_scu_irq_work_handler()
107 scu_irq_wakeup[i].wakeup_src = irq_status & scu_irq_wakeup[i].mask; in imx_scu_irq_work_handler()
123 hdr->ver = IMX_SC_RPC_VERSION; in imx_scu_irq_get_status()
124 hdr->svc = IMX_SC_RPC_SVC_IRQ; in imx_scu_irq_get_status()
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/linux/drivers/dma/lgm/
H A Dlgm-dma.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016 - 2020 Intel Corporation.
10 #include <linux/dma-mapping.h>
23 #include "../virt-dma.h"
25 #define DRIVER_NAME "lgm-dma"
68 #define DMA_MAX_CLASS (SZ_32 - 1)
111 * be configured. It will enable check sum for switch
142 #define DMA_ORRC_MAX_CNT (SZ_32 - 1)
149 #define DMA_MAX_DESC_NUM (SZ_8K - 1)
150 #define DMA_CHAN_BOFF_MAX (SZ_256 - 1)
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/linux/drivers/mfd/
H A Dstmpe.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) ST-Ericsson SA 2010
7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
26 * struct stmpe_platform_data - STMPE platform data
28 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
30 * @autosleep: bool to enable/disable stmpe autosleep
43 return stmpe->variant->enable(stmpe, blocks, true); in __stmpe_enable()
48 return stmpe->variant->enable(stmpe, blocks, false); in __stmpe_disable()
55 ret = stmpe->ci->read_byte(stmpe, reg); in __stmpe_reg_read()
57 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); in __stmpe_reg_read()
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/linux/arch/m68k/include/asm/
H A DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
45 * Mask Revision Register
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
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H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
46 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
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/linux/include/sound/
H A Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
20 /* interrupt0 mask */
22 /* interrupt1 mask */
24 /* DAT mask & DTS select */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
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H A Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */
16 #define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
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/linux/Documentation/devicetree/bindings/regulator/
H A Dti-abb-regulator.txt4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
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/linux/drivers/net/ethernet/hisilicon/hibmcge/
H A Dhbg_hw.c1 // SPDX-License-Identifier: GPL-2.0+
42 if (test_and_set_bit(HBG_NIC_STATE_EVENT_HANDLING, &priv->state)) in hbg_hw_event_notify()
43 return -EBUSY; in hbg_hw_event_notify()
53 clear_bit(HBG_NIC_STATE_EVENT_HANDLING, &priv->state); in hbg_hw_event_notify()
56 dev_err(&priv->pdev->dev, in hbg_hw_event_notify()
64 struct hbg_dev_specs *specs = &priv->dev_specs; in hbg_hw_dev_specs_init()
68 dev_err(&priv->pdev->dev, "dev_specs not init\n"); in hbg_hw_dev_specs_init()
69 return -EINVAL; in hbg_hw_dev_specs_init()
72 specs->mac_id = hbg_reg_read(priv, HBG_REG_MAC_ID_ADDR); in hbg_hw_dev_specs_init()
73 specs->phy_addr = hbg_reg_read(priv, HBG_REG_PHY_ID_ADDR); in hbg_hw_dev_specs_init()
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/linux/sound/soc/intel/catpt/
H A Ddsp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
19 return param == chan->device->dev; in catpt_dma_filter()
33 dma_cap_mask_t mask; in catpt_dma_request_config_chan() local
36 dma_cap_zero(mask); in catpt_dma_request_config_chan()
37 dma_cap_set(DMA_MEMCPY, mask); in catpt_dma_request_config_chan()
39 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); in catpt_dma_request_config_chan()
41 dev_err(cdev->dev, "request channel failed\n"); in catpt_dma_request_config_chan()
42 return ERR_PTR(-ENODEV); in catpt_dma_request_config_chan()
54 dev_err(cdev->dev, "slave config failed: %d\n", ret); in catpt_dma_request_config_chan()
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/linux/include/linux/mfd/
H A Drohm-generic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
40 * struct rohm_dvs_config - dynamic voltage scaling register descriptions
42 * @level_map: bitmap representing supported run-levels for this
45 * @run_mask: value mask for regulator voltages at 'run' state
46 * @run_on_mask: enable mask for regulator at 'run' state
48 * @idle_mask: value mask for regulator voltages at 'idle' state
49 * @idle_on_mask: enable mask for regulator at 'idle' state
51 * @suspend_mask: value mask for regulator voltages at 'suspend' state
52 * @suspend_on_mask: enable mask for regulator at 'suspend' state
54 * @lpsr_mask: value mask for regulator voltages at 'lpsr' state
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/linux/drivers/input/misc/
H A Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
28 /* Regulator master enable addresses */
71 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
107 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
117 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
129 u8 mask, val; in pmic8xxx_pwrkey_shutdown() local
132 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
133 error = pwrkey->shutdown_fn(pwrkey, reset); in pmic8xxx_pwrkey_shutdown()
143 mask = PON_CNTL_1_PULL_UP_EN | PON_CNTL_1_USB_PWR_EN; in pmic8xxx_pwrkey_shutdown()
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/linux/sound/mips/
H A Dad1843.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org>
35 ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */
38 ad1843_RMGE = { 2, 4, 1 }, /* Right ADC Mic Gain Enable */
41 ad1843_LMGE = { 2, 12, 1 }, /* Left ADC Mic Gain Enable */
83 ad1843_DAMIX = { 25, 14, 1 }, /* DAC Digital Mix Enable */
93 ad1843_ADLEN = { 27, 0, 1 }, /* ADC Left Channel Enable */
94 ad1843_ADREN = { 27, 1, 1 }, /* ADC Right Channel Enable */
95 ad1843_AAMEN = { 27, 4, 1 }, /* Analog to Analog Mix Enable */
96 ad1843_ANAEN = { 27, 7, 1 }, /* Analog Channel Enable */
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