Lines Matching +full:enable +full:- +full:mask
2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
71 #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */
72 #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
73 #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
74 #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
75 #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */
87 * Interrupt enable register
91 #define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */
104 #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */
105 #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */
114 #define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */
135 * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i
144 #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */
171 #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */
173 #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Trigger level mask */
182 #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */
198 #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */
200 #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */
254 * (reserved0-3)
270 * (reserved4-5)
273 #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */
274 #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */
285 * the logical OR from per-queue interrupt bits found on SISR registers
300 * NOTE: We don't have per-queue info for this
301 * one, but we can enable it per-queue through
336 * Secondary status registers [5211+] (0 - 4)
338 * These give the status for each QCU, only QCUs 0-9 are
342 #define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
344 #define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
348 #define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
350 #define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
354 #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
368 #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
370 #define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
374 #define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */
378 * Shadow read-and-clear interrupt status registers [5211+]
388 * Interrupt Mask Registers
430 * Secondary interrupt mask registers [5211+] (0 - 4)
433 #define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
435 #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
439 #define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
441 #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
445 #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
459 #define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
461 #define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
465 #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */
469 * DMA Debug registers 0-7
470 * 0xe0 - 0xfc
474 * Decompression mask registers [5212+]
476 #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */
477 #define AR5K_DCM_DATA 0x0404 /*Decompression mask data */
483 #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */
486 #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */
487 #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */
488 #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */
489 #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */
490 #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */
491 #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */
505 #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */
506 #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */
507 #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */
513 #define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */
515 #define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */
516 #define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */
523 #define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */
526 #define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */
545 * Card has 12 TX Queues but i see that only 0-9 are used (?)
547 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
548 * configuration register (0x08c0 - 0x08ec), a ready time configuration
549 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
550 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
551 * global registers, QCU transmit enable/disable and "one shot arm (?)"
567 #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */
571 * QCU Transmit enable register
587 #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */
588 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */
590 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */
597 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */
598 #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */
600 #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */
606 #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */
612 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */
618 #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
619 #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame scheduling mask */
625 #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */
628 #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */
633 #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */
640 #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */
672 * QCU registers in pairs. For each queue we have a QCU mask register,
673 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
674 * a retry limit register (0x1080 - 0x10ac), a channel time register
675 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
676 * a sequence number register (0x1140 - 0x116c). It seems that "global"
683 * DCU QCU mask registers
685 #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */
692 #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */
706 #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */
718 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */
721 #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */
729 * with pending frames. Intra-frame lockout means we wait until
736 #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
737 #define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */
744 #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */
745 #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
747 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
748 #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */
751 #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */
752 #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */
755 #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */
759 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */
794 * and it's used for generating pseudo-random
798 * used for idle sensing -multiplied with cwmin/max etc-)
803 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */
805 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */
807 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */
816 #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */
817 #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */
818 #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */
824 #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */
866 #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */
868 #define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */
895 #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */
896 #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */
897 #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */
898 #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */
908 #define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */
910 #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */
912 #define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */
914 #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */
936 * Mode 0 -> always input
937 * Mode 1 -> output when GPIODO for this GPIO is set to 0
938 * Mode 2 -> output when GPIODO for this GPIO is set to 1
939 * Mode 3 -> always output
948 #define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */
972 #define AR5K_SREV_REV 0x0000000f /* Mask for revision */
974 #define AR5K_SREV_VER 0x000000ff /* Mask for version */
983 * QCU sleep mask
989 * on 5424 and newer pci-e chips. */
993 * register (enable/disable) [5414]
999 * PCI-E Power management configuration
1004 #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1
1008 #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes
1011 #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */
1020 * PCI-E Workaround enable register
1025 * PCI-E Serializer/Deserializer
1036 * Here we got a difference between 5210/5211-12
1043 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
1048 * 5211 - write offset to AR5K_EEPROM_BASE
1054 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
1057 * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
1064 * file posted in madwifi-devel mailing list.
1075 #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
1091 #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
1115 #define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */
1120 * Range 0x7000 - 0x7ce0
1145 #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
1149 #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */
1150 #define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/
1151 #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
1159 #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */
1193 #define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */
1195 #define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */
1202 #define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */
1203 #define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */
1205 #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */
1207 #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
1215 * easier we define a macro based on ah->ah_version for common
1225 #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */
1227 #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */
1229 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */
1231 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */
1233 #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */
1241 #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
1261 #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \
1263 #define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */
1265 #define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */
1267 #define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */
1275 #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \
1283 #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \
1291 #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \
1299 #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \
1307 #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \
1336 #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \
1344 #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \
1359 ((ah->ah_version == AR5K_AR5211 ? \
1362 ((ah->ah_version == AR5K_AR5211 ? \
1370 #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \
1378 #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \
1383 * Transmit mask register (lower 32 bits) [5210]
1388 * Transmit mask register (higher 16 bits) [5210]
1393 * Clear transmit mask [5210]
1410 #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \
1420 #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
1424 #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
1428 #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
1432 #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1434 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */
1436 #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
1440 #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */
1444 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */
1445 #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
1459 #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \
1467 #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \
1481 #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */
1497 * Frame control QoS mask register (?) [5211+]
1503 * Seq mask register (?) [5211+]
1515 * Back-off status register [5210]
1528 #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \
1543 #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \
1551 #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1559 #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \
1567 #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1575 #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \
1598 #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */
1600 #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */
1603 #define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */
1604 #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */
1611 #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */
1613 #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */
1620 #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */
1622 #define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */
1630 #define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */
1641 #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */
1647 #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */
1650 #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enhanced sleep control */
1651 #define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */
1658 #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */
1660 #define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */
1667 #define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */
1669 #define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */
1708 #define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */
1712 #define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */
1714 #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */
1721 #define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */
1759 #define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */
1805 * Range: 0x8147 - 0x818c
1809 * Rate -> ACK SIFS mapping table (32 entries)
1817 * Rate -> duration mapping table (32 entries)
1823 * Rate -> db mapping table
1830 * db -> Rate mapping table
1857 #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */
1859 #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */
1860 #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */
1861 #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */
1883 #define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */
1949 * Pre-Amplifier control register
1950 * (XPA -> external pre-amplifier)
1955 #define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */
1956 #define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */
1971 #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */
1977 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */
2015 #define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */
2016 #define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */
2018 #define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */
2028 #define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */
2085 /* 40MHz -> 5GHz band */
2089 #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
2091 /* 44MHz -> 2.4GHz band */
2094 #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
2155 #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */
2165 #define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */
2177 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */
2179 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */
2181 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */
2182 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */
2187 #define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */
2188 #define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */
2189 #define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */
2190 #define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */
2194 * OFDM Self-correlator Cyclic RSSI threshold params
2198 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */
2199 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */
2202 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */
2207 * PHY-only warm reset register
2212 * PHY-only control register
2222 #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */
2260 #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
2262 /*---[5111+]---*/
2265 #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */
2270 /*---[5110/5111]---*/
2301 5-bits, units unknown {0..31}
2306 6-bits, dBm range {0..63}
2311 6-bits, dBm range {0..63}
2316 6-bits, dBm range {0..63}
2322 7-bits, standard power range
2358 * RF Bus access request register (for synth-only channel switching)
2463 * Heavy clip enable register
2500 #define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */
2504 #define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */
2505 #define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */
2506 #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */
2518 * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]