Lines Matching +full:enable +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
46 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
91 #define CSA_RO 0x8000 /* Read-Only */
93 #define CSB_EN 0x0001 /* Chip-Select Enable */
94 #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
104 #define CSB_RO 0x8000 /* Read-Only */
106 #define CSC_EN 0x0001 /* Chip-Select Enable */
107 #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
117 #define CSC_RO 0x8000 /* Read-Only */
119 #define CSD_EN 0x0001 /* Chip-Select Enable */
120 #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
132 #define CSD_RO 0x8000 /* Read-Only */
135 * Emulation Chip-Select Register
145 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
156 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
163 /* '328-compatible definitions */
188 #define PCTRL_PCEN 0x80 /* Power Control Enable */
192 * 0xFFFFF3xx -- Interrupt Controller
221 * Interrupt Mask Register
236 #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
249 /* '328-compatible definitions */
256 #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
257 #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
258 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
259 #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
260 #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
261 #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
262 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
263 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
264 #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
265 #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
266 #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
267 #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
268 #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
269 #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
270 #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
271 #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
272 #define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
273 #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
275 /* '328-compatible definitions */
291 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
304 /* '328-compatible definitions */
320 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
333 /* '328-compatible definitions */
339 * 0xFFFFF4xx -- Parallel Ports
348 #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
361 #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
385 #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
409 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
412 #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
413 #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
441 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
465 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
489 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
508 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
522 #define PWMC_EN 0x0010 /* Enable PWM */
524 #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
530 /* '328-compatible definitions */
553 * 0xFFFFF6xx -- General-Purpose Timer
563 #define TCTL_TEN 0x0001 /* Timer Enable */
570 #define TCTL_IRQEN 0x0010 /* IRQ Enable */
575 #define TCTL_FRR 0x0010 /* Free-Run Mode */
577 /* '328-compatible definitions */
587 /* '328-compatible definitions */
597 /* '328-compatible definitions */
607 /* '328-compatible definitions */
617 /* '328-compatible definitions */
630 /* '328-compatible definitions */
636 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
656 #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
659 #define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
663 /* '328-compatible definitions */
669 * 0xFFFFF9xx -- UART
679 #define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
680 #define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
681 #define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
682 #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
683 #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
684 #define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
685 #define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
686 #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
687 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
690 #define USTCNT_PEN 0x0800 /* Parity Enable */
692 #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
693 #define USTCNT_RXEN 0x4000 /* Receiver Enable */
694 #define USTCNT_UEN 0x8000 /* UART Enable */
696 /* '328-compatible definitions */
715 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
739 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
762 /* '328-compatible definitions */
774 #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
775 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
778 #define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
780 #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
783 #define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
786 * UART Non-integer Prescaler Register
795 #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
825 * 0xFFFFFAxx -- LCD Controller
835 #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
849 #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
857 #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
907 #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
952 #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
955 #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
957 /* '328-compatible definitions */
1006 #define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
1014 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1063 #define RTCCTL_EN 0x0080 /* RTC Enable */
1065 /* '328-compatible definitions */
1076 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1078 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1080 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1091 * RTC Interrupt Enable Register
1096 #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1097 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1098 #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1099 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1100 #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1101 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1102 #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
1103 #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
1104 #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
1105 #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
1106 #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
1107 #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
1108 #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
1109 #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
1140 * 0xFFFFFCxx -- DRAM Controller
1174 #define DRAMC_DWE 0x0001 /* DRAM Write Enable */
1175 #define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
1176 #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1180 #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1193 #define DRAMC_EN 0x8000 /* DRAM Controller enable */
1198 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1209 * ICE Module Address Mask Register
1224 * ICE Module Control Mask Register
1229 #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
1230 #define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
1238 #define ICEMCR_CEN 0x0001 /* Compare Enable */
1239 #define ICEMCR_PBEN 0x0002 /* Program Break Enable */
1242 #define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
1250 #define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
1251 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */