1 // SPDX-License-Identifier: GPL-2.0+
42 	if (test_and_set_bit(HBG_NIC_STATE_EVENT_HANDLING, &priv->state))  in hbg_hw_event_notify()
43 		return -EBUSY;  in hbg_hw_event_notify()
53 	clear_bit(HBG_NIC_STATE_EVENT_HANDLING, &priv->state);  in hbg_hw_event_notify()
56 		dev_err(&priv->pdev->dev,  in hbg_hw_event_notify()
64 	struct hbg_dev_specs *specs = &priv->dev_specs;  in hbg_hw_dev_specs_init()
68 		dev_err(&priv->pdev->dev, "dev_specs not init\n");  in hbg_hw_dev_specs_init()
69 		return -EINVAL;  in hbg_hw_dev_specs_init()
72 	specs->mac_id = hbg_reg_read(priv, HBG_REG_MAC_ID_ADDR);  in hbg_hw_dev_specs_init()
73 	specs->phy_addr = hbg_reg_read(priv, HBG_REG_PHY_ID_ADDR);  in hbg_hw_dev_specs_init()
74 	specs->mdio_frequency = hbg_reg_read(priv, HBG_REG_MDIO_FREQ_ADDR);  in hbg_hw_dev_specs_init()
75 	specs->max_mtu = hbg_reg_read(priv, HBG_REG_MAX_MTU_ADDR);  in hbg_hw_dev_specs_init()
76 	specs->min_mtu = hbg_reg_read(priv, HBG_REG_MIN_MTU_ADDR);  in hbg_hw_dev_specs_init()
77 	specs->vlan_layers = hbg_reg_read(priv, HBG_REG_VLAN_LAYERS_ADDR);  in hbg_hw_dev_specs_init()
78 	specs->rx_fifo_num = hbg_reg_read(priv, HBG_REG_RX_FIFO_NUM_ADDR);  in hbg_hw_dev_specs_init()
79 	specs->tx_fifo_num = hbg_reg_read(priv, HBG_REG_TX_FIFO_NUM_ADDR);  in hbg_hw_dev_specs_init()
80 	specs->uc_mac_num = hbg_reg_read(priv, HBG_REG_UC_MAC_NUM_ADDR);  in hbg_hw_dev_specs_init()
83 	u64_to_ether_addr(mac_addr, (u8 *)specs->mac_addr.sa_data);  in hbg_hw_dev_specs_init()
85 	if (!is_valid_ether_addr((u8 *)specs->mac_addr.sa_data))  in hbg_hw_dev_specs_init()
86 		return -EADDRNOTAVAIL;  in hbg_hw_dev_specs_init()
88 	specs->max_frame_len = HBG_PCU_CACHE_LINE_SIZE + specs->max_mtu;  in hbg_hw_dev_specs_init()
89 	specs->rx_buf_size = HBG_PACKET_HEAD_SIZE + specs->max_frame_len;  in hbg_hw_dev_specs_init()
107 void hbg_hw_irq_clear(struct hbg_priv *priv, u32 mask)  in hbg_hw_irq_clear()  argument
109 	if (FIELD_GET(HBG_INT_MSK_TX_B, mask))  in hbg_hw_irq_clear()
112 	if (FIELD_GET(HBG_INT_MSK_RX_B, mask))  in hbg_hw_irq_clear()
115 	return hbg_reg_write(priv, HBG_REG_CF_INTRPT_CLR_ADDR, mask);  in hbg_hw_irq_clear()
118 bool hbg_hw_irq_is_enabled(struct hbg_priv *priv, u32 mask)  in hbg_hw_irq_is_enabled()  argument
120 	if (FIELD_GET(HBG_INT_MSK_TX_B, mask))  in hbg_hw_irq_is_enabled()
123 	if (FIELD_GET(HBG_INT_MSK_RX_B, mask))  in hbg_hw_irq_is_enabled()
126 	return hbg_reg_read(priv, HBG_REG_CF_INTRPT_MSK_ADDR) & mask;  in hbg_hw_irq_is_enabled()
129 void hbg_hw_irq_enable(struct hbg_priv *priv, u32 mask, bool enable)  in hbg_hw_irq_enable()  argument
133 	if (FIELD_GET(HBG_INT_MSK_TX_B, mask))  in hbg_hw_irq_enable()
135 				     HBG_REG_CF_IND_TXINT_MSK_ADDR, enable);  in hbg_hw_irq_enable()
137 	if (FIELD_GET(HBG_INT_MSK_RX_B, mask))  in hbg_hw_irq_enable()
139 				     HBG_REG_CF_IND_RXINT_MSK_ADDR, enable);  in hbg_hw_irq_enable()
142 	if (enable)  in hbg_hw_irq_enable()
143 		value |= mask;  in hbg_hw_irq_enable()
145 		value &= ~mask;  in hbg_hw_irq_enable()
187 	frame_len = mtu + VLAN_HLEN * priv->dev_specs.vlan_layers +  in hbg_hw_set_mtu()
197 void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable)  in hbg_hw_mac_enable()  argument
200 			    HBG_REG_PORT_ENABLE_TX_B, enable);  in hbg_hw_mac_enable()
202 			    HBG_REG_PORT_ENABLE_RX_B, enable);  in hbg_hw_mac_enable()
220 	hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_0_ADDR, tx_desc->word0);  in hbg_hw_set_tx_desc()
221 	hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_1_ADDR, tx_desc->word1);  in hbg_hw_set_tx_desc()
222 	hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_2_ADDR, tx_desc->word2);  in hbg_hw_set_tx_desc()
223 	hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_3_ADDR, tx_desc->word3);  in hbg_hw_set_tx_desc()
248 	ret = readl_poll_timeout(priv->io_base + HBG_REG_AN_NEG_STATE_ADDR,  in hbg_hw_adjust_link()
259 void hbg_hw_set_mac_filter_enable(struct hbg_priv *priv, u32 enable)  in hbg_hw_set_mac_filter_enable()  argument
262 			    HBG_REG_REC_FILT_CTRL_UC_MATCH_EN_B, enable);  in hbg_hw_set_mac_filter_enable()
264 	/* only uc filter is supported, so set all bits of mc mask reg to 1 */  in hbg_hw_set_mac_filter_enable()
350 	ctrl |= FIELD_PREP(HBG_REG_RX_CTRL_PORT_NUM, priv->dev_specs.mac_id);  in hbg_hw_init_rx_ctrl()
367 			    HBG_REG_RX_BUF_SIZE_M, priv->dev_specs.rx_buf_size);  in hbg_hw_init_rx_control()