Lines Matching +full:enable +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
45 * Mask Revision Register
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
79 * Group Base Address Mask Registers
91 #define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */
94 * Chip-Select Option Registers (group A)
108 #define CSA_RO 0x00000008 /* Read-Only */
109 #define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
112 #define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
116 * Chip-Select Option Registers (group B)
130 #define CSB_RO 0x00000008 /* Read-Only */
131 #define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
134 #define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
138 * Chip-Select Option Registers (group C)
152 #define CSC_RO 0x00000008 /* Read-Only */
153 #define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
156 #define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
160 * Chip-Select Option Registers (group D)
174 #define CSD_RO 0x00000008 /* Read-Only */
175 #define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
178 #define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
183 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
194 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
200 /* 'EZ328-compatible definitions */
225 #define PCTRL_STOP 0x40 /* Enter power-save mode immediately */
226 #define PCTRL_PCEN 0x80 /* Power Control Enable */
230 * 0xFFFFF3xx -- Interrupt Controller
258 * Interrupt Mask Register
273 #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
291 /* '328-compatible definitions */
298 #define IMR_MSPIM (1 << SPIM_IRQ_NUM) /* Mask SPI Master interrupt */
299 #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
300 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
301 #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
302 #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
303 #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
304 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
305 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
306 #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
307 #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
308 #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
309 #define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */
310 #define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */
311 #define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */
312 #define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */
313 #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
314 #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
315 #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
316 #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
317 #define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */
318 #define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */
319 #define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */
320 #define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */
322 /* 'EZ328-compatible definitions */
327 * Interrupt Wake-Up Enable Register
338 #define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
368 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
386 /* 'EZ328-compatible definitions */
402 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
420 /* 'EZ328-compatible definitions */
426 * 0xFFFFF4xx -- Parallel Ports
442 #define PA_A(x) PA((x) - 16) /* This is specific to PA only! */
501 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
503 #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
530 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
553 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
562 #define PF_A(x) PF((x) - 24) /* This is Port F specific only */
578 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
617 #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */
632 #define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */
644 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
656 #define PWMC_PWMEN 0x0010 /* Enable PWM */
660 #define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */
663 /* 'EZ328-compatible definitions */
686 * 0xFFFFF6xx -- General-Purpose Timers
698 #define TCTL_TEN 0x0001 /* Timer Enable */
705 #define TCTL_IRQEN 0x0010 /* IRQ Enable */
710 #define TCTL_FRR 0x0010 /* Free-Run Mode */
712 /* 'EZ328-compatible definitions */
724 /* 'EZ328-compatible definitions */
736 /* 'EZ328-compatible definitions */
748 /* 'EZ328-compatible definitions */
760 /* 'EZ328-compatible definitions */
775 /* 'EZ328-compatible definitions */
797 #define WCSR_WDEN 0x0001 /* Watchdog Enable */
803 * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
818 #define SPISR_SPISEN 0x0100 /* SPIS module enable */
823 #define SPISR_ENPOL 0x2000 /* Enable Polarity */
824 #define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */
829 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
849 #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
852 #define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */
856 /* 'EZ328-compatible definitions */
861 * 0xFFFFF9xx -- UART
871 #define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */
872 #define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */
873 #define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */
874 #define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */
875 #define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */
876 #define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */
877 #define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */
878 #define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */
879 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
882 #define USTCNT_PARITYEN 0x0800 /* Parity Enable */
884 #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
885 #define USTCNT_RXEN 0x4000 /* Receiver Enable */
886 #define USTCNT_UARTEN 0x8000 /* UART Enable */
888 /* 'EZ328-compatible definitions */
907 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
933 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
955 /* 'EZ328-compatible definitions */
967 #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
968 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
971 #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
1003 * 0xFFFFFAxx -- LCD Controller
1027 #define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */
1035 #define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */
1085 #define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */
1130 #define LCKCON_DWS_MASK 0x3c /* Display Wait-State */
1133 #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
1135 /* 'EZ328-compatible definitions */
1192 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1229 #define RTCCTL_ENABLE 0x0080 /* RTC Enable */
1231 /* 'EZ328-compatible definitions */
1242 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1244 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1248 * RTC Interrupt Enable Register
1253 #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1254 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1255 #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1256 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1257 #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */