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/linux/drivers/clk/qcom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "Eliza Display Clock Controller"
28 Support for the display clock controllers on Eliza SoCs.
29 Say Y if you want to support display devices and functionality such as
33 tristate "Eliza Global Clock Controller"
38 Support for the global clock controller on Eliza devices.
43 tristate "Eliza TCSR Clock Controller"
48 Support for the TCSR clock controller on Eliza devices.
52 tristate "Glymur Camera Clock Controller"
57 Support for the camera clock controller on Qualcomm Technologies, Inc
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/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hitachi HD44780 Character LCD Controller
10 - Geert Uytterhoeven <geert@linux-m68k.org>
13 The Hitachi HD44780 Character LCD Controller is commonly used on character
14 LCDs that can display one or more lines of text. It exposes an M6800 bus
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra186-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display@[0-9a-f]+$"
19 - nvidia,tegra186-dc
20 - nvidia,tegra194-dc
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H A Dnvidia,tegra20-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
19 configuration of the controller takes place at logic configuration bitstream
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H A Dintel,keembay-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/intel,keembay-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay display controller
10 - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
11 - Edmond J Dea <edmund.j.dea@intel.com>
15 const: intel,keembay-display
19 - description: LCD registers range
21 reg-names:
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H A Datmel,lcdc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip's LCDC Display
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
14 The LCD Controller (LCDC) consists of logic for transferring LCD image data
15 from an external display buffer to a TFT LCD panel. The LCDC has one display
17 interface and a look-up table to allow palletized display configurations. The
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/linux/Documentation/gpu/
H A Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
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/linux/Documentation/devicetree/bindings/display/atmel/
H A Datmel,hlcdc-display-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel's High LCD Controller (HLCDC)
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 The LCD Controller (LCDC) consists of logic for transferring LCD image
16 data from an external display buffer to a TFT LCD panel. The LCDC has one
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/linux/drivers/video/fbdev/mmp/hw/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "mmp display controller hw support"
7 Marvell MMP display hw controller support
8 this controller is used on Marvell PXA910 and
12 bool "mmp display controller spi port"
16 Marvell MMP display hw controller spi port support
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,glymur-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Glymur Display MDSS
10 - Abel Vesa <abel.vesa@linaro.org>
13 Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces, etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,glymur-mdss
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H A Dqcom,sm6150-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6150 Display MDSS
10 - Abhinav Kumar <quic_abhinavk@quicinc.com>
11 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
15 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
18 $ref: /schemas/display/msm/mdss-common.yaml#
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H A Dqcom,sm6350-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6350 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6350-mdss
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H A Dqcom,sm6125-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6125 Display MDSS
10 - Marijn Suijten <marijn.suijten@somainline.org>
13 SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6125-mdss
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H A Dqcom,sm6375-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6375 Display MDSS
10 - Konrad Dybcio <konradybcio@kernel.org>
13 SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6375-mdss
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H A Dqcom,sm6115-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6115 Display MDSS
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sm6115-mdss
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H A Dqcom,sc7180-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7180 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7180-mdss
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H A Dqcom,sdm670-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM670 Display MDSS
10 - Richard Acayan <mailingradian@gmail.com>
13 SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sdm670-mdss
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H A Dqcom,sdm845-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM845 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sdm845-mdss
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H A Dqcom,sm8150-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8150 Display MDSS
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
22 - const: qcom,sm8150-mdss
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/linux/drivers/platform/surface/aggregator/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Provides access to a SAM-over-SSH connected EC via a controller device.
10 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
27 #include <linux/surface_aggregator/controller.h>
31 #include "controller.h"
37 /* -- Static controller reference. ------------------------------------------ */
40 * Main controller reference. The corresponding lock must be held while
47 * ssam_get_controller() - Get reference to SSAM controller.
49 * Returns a reference to the SSAM controller of the system or %NULL if there
52 * controller, thus the calling party must ensure that ssam_controller_put()
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
19 display controllers.
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
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/linux/Documentation/devicetree/bindings/gpio/
H A Dxylon,logicvc-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC GPIO controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The LogiCVC GPIO describes the GPIO block included in the LogiCVC display
15 controller. These are meant to be used for controlling display-related
18 The controller exposes GPIOs from the display and power control registers,
20 - GPIO[4:0] (display control) mapped to index 0-4
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/linux/Documentation/fb/
H A Dmetronomefb.rst9 Metronomefb is a driver for the Metronome display controller. The controller
10 is from E-Ink Corporation. It is intended to be used to drive the E-Ink
11 Vizplex display media. E-Ink hosts some details of this controller and the
12 display media here http://www.e-ink.com/products/matrix/metronome.html .
17 The display and error status are each pulled through individual GPIOs.
21 PXA board used in the AM-200 EPD devkit. This example is am200epd.c
24 interface to the metronome controller. The waveform information is expected to
32 a possibility that it could have some permanent effects on the display media.
/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * LCD Controller Registers and Bits Definitions
8 #define LCCR0 (0x000) /* LCD Controller Control Register 0 */
9 #define LCCR1 (0x004) /* LCD Controller Control Register 1 */
10 #define LCCR2 (0x008) /* LCD Controller Control Register 2 */
11 #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
12 #define LCCR4 (0x010) /* LCD Controller Control Register 4 */
13 #define LCCR5 (0x014) /* LCD Controller Control Register 5 */
14 #define LCSR (0x038) /* LCD Controller Status Register 0 */
15 #define LCSR1 (0x034) /* LCD Controller Status Register 1 */
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