Lines Matching +full:display +full:- +full:controller

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * LCD Controller Registers and Bits Definitions
8 #define LCCR0		(0x000)	/* LCD Controller Control Register 0 */
9 #define LCCR1		(0x004)	/* LCD Controller Control Register 1 */
10 #define LCCR2		(0x008)	/* LCD Controller Control Register 2 */
11 #define LCCR3		(0x00C)	/* LCD Controller Control Register 3 */
12 #define LCCR4		(0x010)	/* LCD Controller Control Register 4 */
13 #define LCCR5		(0x014)	/* LCD Controller Control Register 5 */
14 #define LCSR		(0x038)	/* LCD Controller Status Register 0 */
15 #define LCSR1		(0x034)	/* LCD Controller Status Register 1 */
16 #define LIIDR		(0x03C)	/* LCD Controller Interrupt ID Register */
57 #define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
58 #define LCCR0_CMS	(1 << 1)	/* Color/Monochrome Display Select */
59 #define LCCR0_Color	(LCCR0_CMS*0)	/*  Color display */
60 #define LCCR0_Mono	(LCCR0_CMS*1)	/*  Monochrome display */
61 #define LCCR0_SDS	(1 << 2)	/* Single/Dual Panel Display Select */
62 #define LCCR0_Sngl	(LCCR0_SDS*0)	/*  Single panel display */
63 #define LCCR0_Dual	(LCCR0_SDS*1)	/*  Dual panel display */
69 #define LCCR0_PAS	(1 << 7)	/* Passive/Active display Select */
70 #define LCCR0_Pas	(LCCR0_PAS*0)	/*  Passive display (STN) */
71 #define LCCR0_Act	(LCCR0_PAS*1)	/*  Active display (TFT) */
73 #define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome display */
90 #define LCCR1_PPL	Fld (10, 0)	/* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel)	(((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix)	(((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix)	(((Tpix) - 1) << FShft (LCCR1_ELW))
99 #define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock */
100 #define LCCR1_BegLnDel(Tpix)	(((Tpix) - 1) << FShft (LCCR1_BLW))
102 #define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1 */
103 #define LCCR2_DisHght(Line)	(((Line) - 1) << FShft (LCCR2_LPP))
105 #define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse - 1 */
106 #define LCCR2_VrtSnchWdth(Tln)	(((Tln) - 1) << FShft (LCCR2_VSW))
108 #define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait */
111 #define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock */
119 #define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge */
120 #define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge */
161 #define LCSR1_SOF(x)	(1 << ((x) - 1))  /* Start of Frame Status */
166 #define OVLxC1_PPL(x)	((((x) - 1) & 0x3ff) << 0)	/* Pixels Per Line */
167 #define OVLxC1_LPO(x)	((((x) - 1) & 0x3ff) << 10)	/* Number of Lines */