Lines Matching +full:display +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Glymur Display MDSS
10 - Abel Vesa <abel.vesa@linaro.org>
13 Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces, etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,glymur-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
33 - description: Interconnect path from mdp0 port to the data bus
34 - description: Interconnect path from CPU to the reg bus
36 interconnect-names:
38 - const: mdp0-mem
39 - const: cpu-cfg
42 "^display-controller@[0-9a-f]+$":
47 const: qcom,glymur-dpu
49 "^displayport-controller@[0-9a-f]+$":
54 const: qcom,glymur-dp
56 "^phy@[0-9a-f]+$":
61 const: qcom,glymur-dp-phy
64 - compatible
69 - |
70 #include <dt-bindings/clock/qcom,rpmh.h>
71 #include <dt-bindings/interconnect/qcom,icc.h>
72 #include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
73 #include <dt-bindings/interrupt-controller/arm-gic.h>
74 #include <dt-bindings/phy/phy-qcom-qmp.h>
75 #include <dt-bindings/power/qcom,rpmhpd.h>
77 display-subsystem@ae00000 {
78 compatible = "qcom,glymur-mdss";
80 reg-names = "mdss";
87 clock-names = "bus", "nrt_bus", "core";
93 interconnect-names = "mdp0-mem",
94 "cpu-cfg";
98 power-domains = <&mdss_gdsc>;
102 interrupt-controller;
103 #interrupt-cells = <1>;
105 #address-cells = <1>;
106 #size-cells = <1>;
109 display-controller@ae01000 {
110 compatible = "qcom,glymur-dpu";
113 reg-names = "mdp", "vbif";
120 clock-names = "nrt_bus",
126 assigned-clocks = <&dispcc_mdp_vsync_clk>;
127 assigned-clock-rates = <19200000>;
129 operating-points-v2 = <&mdp_opp_table>;
130 power-domains = <&rpmhpd RPMHPD_MMCX>;
132 interrupt-parent = <&mdss>;
136 #address-cells = <1>;
137 #size-cells = <0>;
142 remote-endpoint = <&dsi0_in>;
149 remote-endpoint = <&dsi1_in>;
154 mdp_opp_table: opp-table {
155 compatible = "operating-points-v2";
157 opp-200000000 {
158 opp-hz = /bits/ 64 <200000000>;
159 required-opps = <&rpmhpd_opp_low_svs>;
162 opp-325000000 {
163 opp-hz = /bits/ 64 <325000000>;
164 required-opps = <&rpmhpd_opp_svs>;
167 opp-375000000 {
168 opp-hz = /bits/ 64 <375000000>;
169 required-opps = <&rpmhpd_opp_svs_l1>;
172 opp-514000000 {
173 opp-hz = /bits/ 64 <514000000>;
174 required-opps = <&rpmhpd_opp_nom>;
179 displayport-controller@ae90000 {
180 compatible = "qcom,glymur-dp";
187 interrupt-parent = <&mdss>;
196 clock-names = "core_iface",
203 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
206 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
210 operating-points-v2 = <&mdss_dp0_opp_table>;
212 power-domains = <&rpmhpd RPMHPD_MMCX>;
215 phy-names = "dp";
217 #sound-dai-cells = <0>;
220 #address-cells = <1>;
221 #size-cells = <0>;
227 remote-endpoint = <&mdss_intf0_out>;
239 mdss_dp0_opp_table: opp-table {
240 compatible = "operating-points-v2";
242 opp-160000000 {
243 opp-hz = /bits/ 64 <160000000>;
244 required-opps = <&rpmhpd_opp_low_svs>;
247 opp-270000000 {
248 opp-hz = /bits/ 64 <270000000>;
249 required-opps = <&rpmhpd_opp_svs>;
252 opp-540000000 {
253 opp-hz = /bits/ 64 <540000000>;
254 required-opps = <&rpmhpd_opp_svs_l1>;
257 opp-810000000 {
258 opp-hz = /bits/ 64 <810000000>;
259 required-opps = <&rpmhpd_opp_nom>;