xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml (revision 96c84703f1cf6ea43617f9565166681cd71df104) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6150 Display MDSS
8
9maintainers:
10  - Abhinav Kumar <quic_abhinavk@quicinc.com>
11  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12
13description:
14  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
15  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
16  bindings of MDSS are mentioned for SM6150 target.
17
18$ref: /schemas/display/msm/mdss-common.yaml#
19
20properties:
21  compatible:
22    items:
23      - const: qcom,sm6150-mdss
24
25  clocks:
26    items:
27      - description: Display AHB clock from gcc
28      - description: Display hf axi clock
29      - description: Display core clock
30
31  clock-names:
32    items:
33      - const: iface
34      - const: bus
35      - const: core
36
37  iommus:
38    maxItems: 1
39
40  interconnects:
41    maxItems: 2
42
43  interconnect-names:
44    maxItems: 2
45
46patternProperties:
47  "^display-controller@[0-9a-f]+$":
48    type: object
49    additionalProperties: true
50    properties:
51      compatible:
52        const: qcom,sm6150-dpu
53
54  "^dsi@[0-9a-f]+$":
55    type: object
56    additionalProperties: true
57    properties:
58      compatible:
59        items:
60          - const: qcom,sm6150-dsi-ctrl
61          - const: qcom,mdss-dsi-ctrl
62
63  "^phy@[0-9a-f]+$":
64    type: object
65    additionalProperties: true
66    properties:
67      compatible:
68        const: qcom,sm6150-dsi-phy-14nm
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,rpmh.h>
75    #include <dt-bindings/interconnect/qcom,icc.h>
76    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78    #include <dt-bindings/power/qcom,rpmhpd.h>
79
80    display-subsystem@ae00000 {
81        #address-cells = <1>;
82        #size-cells = <1>;
83        compatible = "qcom,sm6150-mdss";
84        reg = <0x0ae00000 0x1000>;
85        reg-names = "mdss";
86
87        interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
88                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
89                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
90                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
91        interconnect-names = "mdp0-mem", "cpu-cfg";
92
93        power-domains = <&dispcc_mdss_gdsc>;
94
95        clocks = <&dispcc_mdss_ahb_clk>,
96                 <&gcc_disp_hf_axi_clk>,
97                 <&dispcc_mdss_mdp_clk>;
98
99        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
100        interrupt-controller;
101        #interrupt-cells = <1>;
102
103        iommus = <&apps_smmu 0x800 0x0>;
104
105        ranges;
106
107        display-controller@ae01000 {
108            compatible = "qcom,sm6150-dpu";
109            reg = <0x0ae01000 0x8f000>,
110                  <0x0aeb0000 0x2008>;
111            reg-names = "mdp", "vbif";
112
113            clocks = <&dispcc_mdss_ahb_clk>,
114                     <&gcc_disp_hf_axi_clk>,
115                     <&dispcc_mdss_mdp_clk>,
116                     <&dispcc_mdss_vsync_clk>;
117            clock-names = "iface", "bus", "core", "vsync";
118
119            assigned-clocks = <&dispcc_mdss_vsync_clk>;
120            assigned-clock-rates = <19200000>;
121
122            operating-points-v2 = <&mdp_opp_table>;
123            power-domains = <&rpmhpd RPMHPD_CX>;
124
125            interrupt-parent = <&mdss>;
126            interrupts = <0>;
127
128            ports {
129                #address-cells = <1>;
130                #size-cells = <0>;
131
132                port@0 {
133                  reg = <0>;
134                  dpu_intf0_out: endpoint {
135                  };
136                };
137
138                port@1 {
139                  reg = <1>;
140                  dpu_intf1_out: endpoint {
141                      remote-endpoint = <&mdss_dsi0_in>;
142                  };
143                };
144            };
145
146            mdp_opp_table: opp-table {
147                compatible = "operating-points-v2";
148
149                opp-19200000 {
150                  opp-hz = /bits/ 64 <19200000>;
151                  required-opps = <&rpmhpd_opp_low_svs>;
152                };
153
154                opp-25600000 {
155                  opp-hz = /bits/ 64 <25600000>;
156                  required-opps = <&rpmhpd_opp_svs>;
157                };
158
159                opp-307200000 {
160                  opp-hz = /bits/ 64 <307200000>;
161                  required-opps = <&rpmhpd_opp_nom>;
162                };
163            };
164        };
165
166        dsi@ae94000 {
167            compatible = "qcom,sm6150-dsi-ctrl",
168                         "qcom,mdss-dsi-ctrl";
169            reg = <0x0ae94000 0x400>;
170            reg-names = "dsi_ctrl";
171
172            interrupt-parent = <&mdss>;
173            interrupts = <4>;
174
175            clocks = <&dispcc_mdss_byte0_clk>,
176                     <&dispcc_mdss_byte0_intf_clk>,
177                     <&dispcc_mdss_pclk0_clk>,
178                     <&dispcc_mdss_esc0_clk>,
179                     <&dispcc_mdss_ahb_clk>,
180                     <&gcc_disp_hf_axi_clk>;
181            clock-names = "byte",
182                          "byte_intf",
183                          "pixel",
184                          "core",
185                          "iface",
186                          "bus";
187
188            assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
189                              <&dispcc_mdss_pclk0_clk_src>;
190            assigned-clock-parents = <&mdss_dsi0_phy 0>,
191                                     <&mdss_dsi0_phy 1>;
192
193            operating-points-v2 = <&dsi0_opp_table>;
194
195            phys = <&mdss_dsi0_phy>;
196
197            #address-cells = <1>;
198            #size-cells = <0>;
199
200            ports {
201                #address-cells = <1>;
202                #size-cells = <0>;
203
204                port@0 {
205                    reg = <0>;
206                    mdss_dsi0_in: endpoint {
207                        remote-endpoint = <&dpu_intf1_out>;
208                    };
209                };
210
211                port@1 {
212                    reg = <1>;
213                    mdss_dsi0_out: endpoint {
214                    };
215                };
216            };
217
218            dsi0_opp_table: opp-table {
219                compatible = "operating-points-v2";
220
221                opp-164000000 {
222                    opp-hz = /bits/ 64 <164000000>;
223                    required-opps = <&rpmhpd_opp_low_svs>;
224                };
225            };
226        };
227
228        mdss_dsi0_phy: phy@ae94400 {
229            compatible = "qcom,sm6150-dsi-phy-14nm";
230            reg = <0x0ae94400 0x100>,
231                  <0x0ae94500 0x300>,
232                  <0x0ae94800 0x188>;
233            reg-names = "dsi_phy",
234                        "dsi_phy_lane",
235                        "dsi_pll";
236
237            #clock-cells = <1>;
238            #phy-cells = <0>;
239
240            clocks = <&dispcc_mdss_ahb_clk>,
241                     <&rpmhcc RPMH_CXO_CLK>;
242            clock-names = "iface", "ref";
243        };
244    };
245...
246