Home
last modified time | relevance | path

Searched +full:ddr +full:- +full:config (Results 1 – 25 of 176) sorted by relevance

12345678

/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 config ARM_CCI_PMU
17 If compiled as a module, it will be called arm-cci.
19 config ARM_CCI400_PMU
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
28 config ARM_CCI5xx_PMU
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
37 config ARM_CCN
[all …]
/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
17 config DDR config
20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
25 config ARM_PL172_MPMC
33 config ATMEL_EBI
42 Used to configure the EBI (external bus interface) when the device-
46 config BRCMSTB_DPFE
52 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
[all …]
H A Dbrcmstb_memc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
39 void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG; in brcmstb_memc_uses_lpddr4() local
42 reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK; in brcmstb_memc_uses_lpddr4()
50 void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset; in brcmstb_memc_srpd_config()
55 return -EINVAL; in brcmstb_memc_srpd_config()
57 memc->timeout_cycles = cycles; in brcmstb_memc_srpd_config()
75 return sprintf(buf, "%d\n", memc->frequency); in frequency_show()
83 return sprintf(buf, "%d\n", memc->timeout_cycles); in srpd_show()
99 return -EOPNOTSUPP; in srpd_store()
[all …]
/linux/sound/soc/sprd/
H A Dsprd-pcm-compress.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/dma-mapping.h>
6 #include <linux/dma/sprd-dma.h>
14 #include "sprd-pcm-dma.h"
31 #define SPRD_COMPR_IRAM_LINKLIST_SIZE (1024 - SPRD_COMPR_IRAM_INFO_SIZE)
36 /* Stage 1 DDR buffer size definition */
52 * The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to
58 * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
59 * power-on) and DDR buffer. The source channel will transfer data from IRAM
62 * DDR buffer to IRAM buffer.
[all …]
/linux/arch/arm/mach-imx/
H A Dsuspend-imx53.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
44 /* Save pad config */
60 /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */
66 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */
72 /* Set pad config */
99 /* Restore pad config */
115 /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */
121 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */
134 .word . - imx53_suspend
/linux/drivers/memory/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config TEGRA_MC
13 config TEGRA20_EMC
19 select DDR
26 config TEGRA30_EMC
31 select DDR
38 config TEGRA124_EMC
50 config TEGRA210_EMC_TABLE
54 config TEGRA210_EMC
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx7ulp-pinctrl.txt4 ports and IOMUXC DDR for DDR interface.
8 supports generic pin config.
10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
14 - compatible: "fsl,imx7ulp-iomuxc1".
15 - fsl,pins: Each entry consists of 5 integers which represents the mux
16 and config setting for one pin. The first 4 integers
19 imx7ulp-pinfunc.h in the device tree source folder.
20 The last integer CONFIG is the pad setting value like
21 pull-up on this pin.
24 CONFIG settings.
[all …]
/linux/drivers/clk/sophgo/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 config CLK_SOPHGO_CV1800
13 config CLK_SOPHGO_SG2042_PLL
20 PLL, DDR PLL 0 and DDR PLL 1 respectively.
22 config CLK_SOPHGO_SG2042_CLKGEN
31 config CLK_SOPHGO_SG2042_RPGATE
/linux/drivers/mtd/lpddr/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 config MTD_LPDDR
10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
13 config MTD_QINFO_PROBE
22 config MTD_LPDDR2_NVM
25 tristate "Support for LPDDR2-NVM flash chips"
27 This option enables support of PCM memories with a LPDDR2-NVM
/linux/drivers/clk/baikal-t1/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config CLK_BAIKAL_T1
3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
17 config CLK_BT1_CCU_PLL
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
30 config CLK_BT1_CCU_DIV
[all …]
/linux/drivers/devfreq/event/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
17 config DEVFREQ_EVENT_EXYNOS_NOCP
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
26 config DEVFREQ_EVENT_EXYNOS_PPMU
31 This add the devfreq-event driver for Exynos SoC. It provides PPMU
[all …]
H A Drockchip-dfi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
8 #include <linux/devfreq-event.h>
69 * struct dmc_count_channel - structure to hold counter values from the DDR controller
71 * @clock_cycles: DDR clock cycles
87 * The dfi controller can monitor DDR load. It has an upper and lower threshold
89 * generated to indicate the DDR frequency should be changed.
123 void __iomem *dfi_regs = dfi->regs; in rockchip_dfi_enable()
126 mutex_lock(&dfi->mutex); in rockchip_dfi_enable()
128 dfi->usecount++; in rockchip_dfi_enable()
[all …]
/linux/Documentation/admin-guide/perf/
H A Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
10 Selection of the value for each counter is done via the config registers. There
16 The "format" directory describes format of the config (event ID) and config1/2
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
33 un-supported, and value 1 for supported.
37 --AXI_ID defines AxID matching value.
[all …]
/linux/arch/mips/mti-malta/
H A Dmalta-dtshim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <asm/mips-boards/generic.h>
16 #include <asm/mips-boards/malta.h>
17 #include <asm/mips-cps.h>
83 * DDR but limits it to 2GB. in gen_fdt_mem_array()
91 size -= size_preio; in gen_fdt_mem_array()
97 * We have a flat 32 bit physical memory map with DDR filling in gen_fdt_mem_array()
99 * obscures 256MB from 0x10000000-0x1fffffff. in gen_fdt_mem_array()
105 size -= SZ_256M; in gen_fdt_mem_array()
113 * We have a 32 bit physical memory map with a 2GB DDR region in gen_fdt_mem_array()
[all …]
/linux/drivers/perf/amlogic/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config MESON_DDR_PMU
3 tristate "Amlogic DDR Bandwidth Performance Monitor"
6 Provides support for the DDR performance monitor
/linux/include/linux/platform_data/
H A Demif_plat.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Low power modes - EMIF_PWR_MGMT_CTRL */
23 * EMIF4D - Used in OMAP4
24 * EMIF4D5 - Used in OMAP5
31 * ATTILAPHY - Used in OMAP4
32 * INTELLIPHY - Used in OMAP5
37 /* Custom config requests */
44 * struct ddr_device_info - All information about the DDR device except AC
46 * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc)
49 * @cs1_used: Whether there is a DDR device attached to the second
[all …]
/linux/drivers/media/pci/cx18/
H A Dcx18-cards.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from ivtv-cards.c
11 #include "cx18-driver.h"
12 #include "cx18-cards.h"
13 #include "cx18-av-core.h"
14 #include "cx18-i2c.h"
38 /* Please add new PCI IDs to: https://pci-ids.ucw.cz/
43 /* Hauppauge HVR-1600 cards */
49 .name = "Hauppauge HVR-1600",
74 .ddr = {
[all …]
H A Dcx18-cards.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Derived from ivtv-cards.c
98 struct cx18_ddr { /* DDR config data */
121 /* GPIO card-specific settings */
130 struct cx18_ddr ddr; member
/linux/drivers/perf/hisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config HISI_PMU
7 Agent performance monitor and DDR Controller performance monitor.
9 config HISI_PCIE_PMU
18 config HNS3_PMU
/linux/arch/arc/plat-axs10x/
H A Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
33 * --------------------- in axs10x_enable_gpio_intc_wire()
34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
35 * --------------------- in axs10x_enable_gpio_intc_wire()
37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
39 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
43 * ------------------------ in axs10x_enable_gpio_intc_wire()
[all …]
/linux/drivers/dma/qcom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config QCOM_ADM
11 and on-chip peripheral devices.
13 config QCOM_BAM_DMA
20 provides DMA capabilities for a variety of on-chip devices.
22 config QCOM_GPI_DMA
32 transfer data between DDR and peripheral.
34 config QCOM_HIDMA_MGMT
46 config QCOM_HIDMA
/linux/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 /* machine-specific reboot/halt operation */
25 /* loongson-specific command line, env and memory initialization */
62 #define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
66 #define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
70 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
73 #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
77 #define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
84 #define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
88 #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
[all …]
/linux/drivers/memory/samsung/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 config SAMSUNG_MC
10 config EXYNOS5422_DMC
13 select DDR
24 config EXYNOS_SROM
/linux/drivers/soc/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 config KEYSTONE_NAVIGATOR_QMSS
18 Packets are queued/de-queued by writing/reading descriptor address
23 config KEYSTONE_NAVIGATOR_DMA
33 config AMX3_PM
40 c-states on AM335x. Also required for rtc and ddr in self-refresh low
43 config WKUP_M3_IPC
44 tristate "TI AMx3 Wkup-M3 IPC Driver"
53 config TI_K3_RINGACC
64 config TI_K3_SOCINFO
[all …]
/linux/Documentation/arch/arm/stm32/
H A Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
60 case, the linked-list loops on to create a circular MDMA transfer.
[all …]

12345678