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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-msm.txt1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
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H A Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx7ulp-pinctrl.txt4 ports and IOMUXC DDR for DDR interface.
8 supports generic pin config.
10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
14 - compatible: "fsl,imx7ulp-iomuxc1".
15 - fsl,pins: Each entry consists of 5 integers which represents the mux
16 and config setting for one pin. The first 4 integers
19 imx7ulp-pinfunc.h in the device tree source folder.
20 The last integer CONFIG is the pad setting value like
21 pull-up on this pin.
24 CONFIG settings.
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/illumos-gate/usr/src/uts/common/sys/ib/adapters/tavor/
H A Dtavor_srq.h50 * (SRQ) and their maximum size. Settings exist for the supported DDR DIMM
52 * 256MB profile is used. See tavor_cfg.c for more discussion on config
55 * For manual configuration (not using config profiles), these values are
57 * configuration variables, respectively. To override config profile settings
80 * use in the config profile to be 0xF. This can still be overridden with the
81 * patchable variable in the config profile.
88 * the SRQ memory is in DDR memory (no sync) or system memory (sync required).
91 * of the "sync override" parameter in the config profile.
94 ((((((state)->ts_cfg_profile->cp_streaming_consistent) && \
95 ((state)->ts_cfg_profile->cp_consistent_syncoverride))) || \
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H A Dtavor_qp.h52 * their maximum size. Settings exist for the supported DDR DIMM sizes of
54 * profile is used. See tavor_cfg.c for more discussion on config profiles.
56 * For manual configuration (not using config profiles), these values are
58 * configuration variables, respectively. To override config profile settings
80 * the QP memory is in DDR memory (no sync) or system memory (sync required).
83 * "sync override" parameter in the config profile.
86 ((((((state)->ts_cfg_profile->cp_streaming_consistent) && \
87 ((state)->ts_cfg_profile->cp_consistent_syncoverride))) || \
103 * entries (RDB). Settings exist for the supported DDR DIMM sizes of 128MB and
105 * See tavor_cfg.c for more discussion on config profiles.
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H A Dtavor_cq.h54 * their maximum size. Settings exist for the supported DDR DIMM sizes of
56 * profile is used. See tavor_cfg.c for more discussion on config profiles.
58 * For manual configuration (not using config profiles), these values are
60 * configuration variables, respectively. To override config profile settings
82 * the CQ memory is in DDR memory (no sync) or system memory (sync required).
83 * Note: It doesn't make much sense to put CQEs in DDR memory (since they are
87 * sync'd because of the "sync override" parameter in the config profile.
90 ((((((state)->ts_cfg_profile->cp_streaming_consistent) && \
91 ((state)->ts_cfg_profile->cp_consistent_syncoverride))) || \
H A Dtavor.h89 ((1 << TAVOR_MINORNUM_SHIFT) - 1))
92 * Locations for the various Tavor hardware PCI BARs (CMD, UAR, DDR)
101 * beginning to poll for completion (TAVOR_SW_RESET_DELAY), the in-between
113 * also specify two config registers which should not be read or restored.
128 cmn_err(CE_WARN, "tavor%d: "string, (state)->ts_instance)
148 * softstate. When "ts_ibtfpriv" is non-NULL, it is OK to forward asynch
163 (state)->ts_ibtfpriv = (tmp_ibtfpriv);
166 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS((state)->ts_in_evcallb)) \
167 (state)->ts_in_evcallb = 1; \
168 ibc_async_handler((state)->ts_ibtfpriv, (type), (event)); \
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H A Dtavor_mr.h51 * individual entry size. Settings exist for the supported DDR DIMM sizes of
53 * profile is used. See tavor_cfg.c for more discussion on config profiles.
55 * For manual configuration (not using config profiles), this value is
57 * override config profile settings the 'tavor_alt_config_enable' configuration
82 * default value is used to initialize the "tavor_log_num_mttseg" config
99 (((num) + TAVOR_MTTSEG_SIZE - 1) >> \
110 * set depending on size of the DDR being either 128MB or 256MB. These defines
146 (((mr)->mr_bindinfo.bi_bypass != TAVOR_BINDMEM_BYPASS) || \
175 #define TAVOR_MTT_REFCNT_INIT(swrc_tmp) ((swrc_tmp)->swrc_refcnt = 1)
176 #define TAVOR_MTT_IS_NOT_SHARED(swrc_tmp) ((swrc_tmp)->swrc_refcnt == 1)
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H A Dtavor_event.h51 * If on a 32-bit system, we must hold a lock around the ddi_put64() to
52 * ensure that the 64-bit write is an atomic operation. This is a
55 * of their two 32-bit accesses (for 64-bit doorbell) simultaneously.
57 * If we are on a 64-bit system then the ddi_put64() is completed as one
58 * 64-bit instruction, and the lock is not needed.
60 * This is done as a preprocessor #if to speed up execution at run-time
61 * since doorbell ringing is a "fast-path" operation.
65 mutex_enter(&state->ts_uar_lock); \
66 ddi_put64(state->ts_reg_uarhdl, ts_uar, doorbell); \
67 mutex_exit(&state->ts_uar_lock); \
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/illumos-gate/usr/src/uts/common/io/ib/adapters/tavor/
H A Dtavor_cfg.c45 /* Set to enable alternative configurations: 0 = automatic config, 1 = manual */
133 * Whether or not to use the built-in (i.e. in firmware) agents for QP0 and
155 * NON-COHERENT) will necessarily turn off BYPASS for that registration. To
166 * from Tavor DDR memory. Note: 0 for system memory, 1 for DDR memory
172 * from Tavor DDR memory. Note: 0 for system memory, 1 for DDR memory
184 * initiating SW reset before we do our first read from Tavor config space.
186 * possible for Tavor hardware to be unready to respond to the config cycle
195 * the number of usec to wait in-between calls to poll the 'go' bit. The
216 * default (least common denominator - one (1) PCI read) behavior that is
219 * field in the "PCI-X Command Register".
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H A Dtavor_rsrc.c33 * by Tavor hardware or which live in Tavor's direct attached DDR memory.
55 * be allocated from Tavor's direct attached DDR memory or from system
56 * memory (although currently all "In" mailboxes are in DDR and all "out"
66 * to come from DDR memory, they are always allocated from tables, and
72 * of which are also required to reside in DDR memory and are not to be
76 * allocated from the UAR address space rather than DDR, and the UD
188 rsrc_pool = &state->ts_rsrc_hdl[rsrc]; in tavor_rsrc_alloc()
195 tmp_rsrc_hdl = (tavor_rsrc_t *)kmem_cache_alloc(state->ts_rsrc_cache, in tavor_rsrc_alloc()
206 tmp_rsrc_hdl->rsrc_type = rsrc; in tavor_rsrc_alloc()
211 switch (rsrc_pool->rsrc_type) { in tavor_rsrc_alloc()
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H A Dtavor.c250 *result = (void *)state->ts_dip; in tavor_getinfo()
320 * an explicit mutex_enter of the database lock - "tdl_umapdb_lock") in tavor_open()
341 if (!TAVOR_IS_OPERATIONAL(state->ts_operational_mode)) { in tavor_open()
343 tr_indx = state->ts_open_tr_indx++; in tavor_open()
354 tr_indx = rsrcp->tr_indx; in tavor_open()
366 if (TAVOR_IS_OPERATIONAL(state->ts_operational_mode)) { in tavor_open()
391 if (TAVOR_IS_OPERATIONAL(state->ts_operational_mode)) { in tavor_open()
408 dev = makedevice(getmajor(*devp), (rsrcp->tr_indx << in tavor_open()
468 * If the "tdb_priv" field is non-NULL, it indicates that in tavor_close()
475 priv = (tavor_umap_db_priv_t *)umapdb->tdbe_common.tdb_priv; in tavor_close()
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/illumos-gate/usr/src/uts/common/io/ntxn/
H A Dunm_brdcfg.h72 /* Dual CX4 - Low Profile - Red card */
146 /* MN-related config */
167 __uint32_t mn_mode_reg; /* See MIU DDR Mode Register */
168 __uint32_t mn_ext_mode_reg; /* See MIU DDR Extended Mode Register */
173 /* SN-related config */
257 BRDCFG_START = 0x4000, /* board config */
/illumos-gate/usr/src/man/man8/
H A Dipsecconf.88 ipsecconf \- configure system wide IPsec policy
16 \fB/usr/sbin/ipsecconf\fR \fB-a\fR \fIfile\fR [\fB-q\fR]
21 \fB/usr/sbin/ipsecconf\fR \fB-c\fR \fIfile\fR
26 \fB/usr/sbin/ipsecconf\fR \fB-d\fR [\fB-i\fR \fItunnel-name\fR] {\fIindex\fR, \fItunnel-name\fR, \…
31 \fB/usr/sbin/ipsecconf\fR \fB-f\fR [\fB-i\fR \fItunnel-name\fR]
36 \fB/usr/sbin/ipsecconf\fR \fB-F\fR
41 \fB/usr/sbin/ipsecconf\fR \fB-l\fR [\fB-i\fR \fItunnel-name\fR] [\fB-n\fR]
46 \fB/usr/sbin/ipsecconf\fR \fB-L\fR [\fB-n\fR]
73 entries loaded are shown. To display the (\fBspd p.e.\fRs) use the \fB-l\fR
75 tunnel's SPD, use the \fB-i\fR option in combination with \fB-l\fR. To specify
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
299 uint32_t config; member
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other…
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/illumos-gate/usr/src/lib/libjedec/common/
H A Dlibjedec.h23 * o JEDEC JEP-106 vendor data
25 * (JESD402-1)
47 * JEDEC operating temperature ranges. These are defined in JESD402-1B
127 * parse the overall SPD data structure. These represent a top-level failure and
162 * categories. Fatal errors set a value in the spd_error_t below. Non-fatal
166 * The keys are all dot delineated to create a few different top-level
169 * "meta" -- Which includes information about the SPD, encoding, and things like
172 * "dram" -- Parameters that are specific to the SDRAM dies present. What one
177 * "channel" -- Parameters that are tied to an implementation of a channel. DDR4
179 * sub-channels.
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Db4860si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
45 #address-cells = <2>;
46 #size-cells = <2>;
47 fsl,iommu-parent = <&pamu0>;
51 #address-cells = <2>;
52 #size-cells = <2>;
53 cell-index = <1>;
57 #address-cells = <2>;
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H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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/illumos-gate/usr/src/cmd/fm/schemes/mem/
H A Dmem_spd.h31 * Layout of SPD-format data, as per PICL.
43 uint8_t memory_type; /* e.g. SDRAM DDR = 0x07 */
52 uint8_t config; /* e.g. ECC = 0x02 */ member
77 uint8_t superset[62 - 36];
82 uint8_t manu_part_no[91 - 73];
88 uint8_t manu_specific[128 - 99];
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
[all …]
/freebsd/sys/dev/sfxge/common/
H A Defx_regs_mcdi_aoe.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2018 Solarflare Communications Inc. All rights reserved.
152 /* enum: PHY read connection from FC - may be not required */
154 /* enum: PHY read flags from FC - may be not required */
172 /* enum: MAC Set command - same as MC_CMD_SET_MAC */
186 /* enum: Internal Siena-facing FPGA ports. */
357 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */
413 /* Clear previous test result and prepare for restarting DDR test */
573 /* enum: Get loopback mode config state on fpga port */
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/illumos-gate/usr/src/uts/common/sys/ib/adapters/hermon/
H A Dhermon.h91 ((1 << HERMON_MINORNUM_SHIFT) - 1))
96 #define HERMON_CMD_BAR 1 /* device config space */
98 #define HERMON_MSIX_BAR 3 /* MSI-X Table */
105 * VPD header size - or more rightfully, the area of interest for fwflash
121 * beginning to poll for completion (HERMON_SW_RESET_DELAY), the in-between
133 * also specify two config registers which should not be read or restored.
151 cmn_err(CE_CONT, "!hermon%d: %s\n", (state)->hs_instance, string)
171 * softstate. When "hs_ibtfpriv" is non-NULL, it is OK to forward asynch
186 (state)->hs_ibtfpriv = (tmp_ibtfpriv);
189 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS((state)->hs_in_evcallb)) \
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