Lines Matching +full:ddr +full:- +full:config
2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
10 Selection of the value for each counter is done via the config registers. There
16 The "format" directory describes format of the config (event ID) and config1/2
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
33 un-supported, and value 1 for supported.
37 --AXI_ID defines AxID matching value.
38 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
40 - 0: corresponding bit is masked.
41 - 1: corresponding bit is not masked, i.e. used to do the matching.
44 When non-masked bits are matching corresponding AXI_ID bits then counter is
49 This filter doesn't support filter different AXI ID for axid-read and axid-write
52 .. code-block:: bash
54 perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
55 perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
63 .. code-block:: bash
65 perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
69 counting the number of bytes (as opposed to the number of bursts) from DDR
75 extension of AXI ID filter. One improvement is that counter 1-3 has their own
77 improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support
80 Filter is defined with 2 configuration registers per counter 1-3.
81 --Counter N MASK COMP register - including AXI_ID and AXI_MASKING.
82 --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.
84 - 0: address channel
85 - 1: data channel
87 PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved
90 .. code-block:: bash
92 perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd
93 perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd
99 monitor data channel from DDR transactions, since data channel is more