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/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A Dfloating-point.json16 "CounterHTOff": "0,1,2,3,4,5,6,7",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
46 "CounterHTOff": "0,1,2,3,4,5,6,7",
54 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
59 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
64 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
66 "CounterHTOff": "0,1,2,3,4,5,6,7",
69 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
[all …]
H A Dfrontend.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "CounterHTOff": "0,1,2,3,4,5,6,7",
53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB…
55 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
H A Dvirtual-memory.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
34 "CounterHTOff": "0,1,2,3,4,5,6,7",
44 "CounterHTOff": "0,1,2,3,4,5,6,7",
47 "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
54 "CounterHTOff": "0,1,2,3,4,5,6,7",
64 "CounterHTOff": "0,1,2,3,4,5,6,7",
74 "CounterHTOff": "0,1,2,3,4,5,6,7",
84 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Dfloating-point.json16 "CounterHTOff": "0,1,2,3,4,5,6,7",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
46 "CounterHTOff": "0,1,2,3,4,5,6,7",
54 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
59 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
64 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
66 "CounterHTOff": "0,1,2,3,4,5,6,7",
69 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
[all …]
H A Dfrontend.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "CounterHTOff": "0,1,2,3,4,5,6,7",
53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB…
55 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Dfloating-point.json15 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
49 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
51 "CounterHTOff": "0,1,2,3,4,5,6,7",
58 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issue…
69 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A Dfloating-point.json15 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
49 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
51 "CounterHTOff": "0,1,2,3,4,5,6,7",
58 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issue…
69 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td1 //===- P9InstrResources.td - P9 Instruction Resource Defs -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // - Each CPU is made up of two superslices.
17 // - Each superslice is made up of two slices. Therefore, there are 4 slices
19 // - Up to 6 instructions can be dispatched to each CPU. Three per superslice.
20 // - Each CPU has:
21 // - One CY (Crypto) unit P9_CY_*
22 // - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
23 // - Two PM (Permute) units. One on each superslice. P9_PM_*
[all …]
H A DPPCScheduleP9.td1 //===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
5 // SPDX-Licens
[all...]
H A DPPCScheduleP7.td1 //===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===//
5 // SPDX-Licens
[all...]
/freebsd/lib/libpmc/pmu-events/arch/x86/alderlake/
H A Dpipeline.json180 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
214 …e number of issue slots not consumed due to a micro-sequencer (MS) scoreboard, which stalls the fr…
235 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
257 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
268 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
279 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by …
289 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
300 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
311 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
322 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmc-nor.txt8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
19 - gpmc,we-on-ns Write-enable assertion time
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A Dfrontend.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
31 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
40 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
51 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A Dfrontend.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
31 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
40 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
51 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A Dvirtual-memory.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
46 "CounterHTOff": "0,1,2,3,4,5,6,7",
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
66 "CounterHTOff": "0,1,2,3,4,5,6,7",
74 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT…
76 "CounterHTOff": "0,1,2,3,4,5,6,7",
79 …"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EP…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylake/
H A Dvirtual-memory.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
46 "CounterHTOff": "0,1,2,3,4,5,6,7",
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
66 "CounterHTOff": "0,1,2,3,4,5,6,7",
74 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT…
76 "CounterHTOff": "0,1,2,3,4,5,6,7",
79 …"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EP…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A Dvirtual-memory.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
46 "CounterHTOff": "0,1,2,3,4,5,6,7",
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
66 "CounterHTOff": "0,1,2,3,4,5,6,7",
74 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT…
76 "CounterHTOff": "0,1,2,3,4,5,6,7",
79 …"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EP…
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dgpmc-eth.txt4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
[all …]
/freebsd/contrib/lua/src/
H A Dlgc.h22 ** can be visited again before finishing the collection cycle. (Open
37 #define GCSswpend 6
43 (GCSswpallgc <= (g)->gcstate && (g)->gcstate <= GCSswpend)
50 ** still-black objects. The invariant is restored when sweep ends and
54 #define keepinvariant(g) ((g)->gcstate <= GCSatomic)
78 #define FINALIZEDBIT 6 /* object has been marked for finalization */
87 #define iswhite(x) testbits((x)->marked, WHITEBITS)
88 #define isblack(x) testbit((x)->marked, BLACKBIT)
90 (!testbits((x)->marked, WHITEBITS | bitmask(BLACKBIT)))
92 #define tofinalize(x) testbit((x)->marked, FINALIZEDBIT)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3430-sdp.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3";
20 clock-frequency = <2600000>;
32 vmmc-supply = <&vmmc1>;
33 vqmmc-supply = <&vsim>;
35 * S6-3 must be in ON position for 8 bit mode to function
38 bus-width = <8>;
55 compatible = "cfi-flash";
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedOryon.td1 //=- AArch64SchedOryon.td - Qualcomm Oryon CPU 001 ---*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
36 // IXU has 6 ports p0 ~ p5
75 // Port 6: Load/Store. LS0
139 // Multiply/Multiply-ADD instructions on ports I4/I5.
165 // Arithmetic and CRYP-AED ASIMD/FP instructions on ports FP0/FP1/FP2/FP3.
181 // CRYP-SHA instructions on ports FP1.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.txt4 external memory (such as NAND or other memory-mapped peripherals) whereas
10 NOR flash memories), WE (write enable). This on top of 6 different chip selects
11 (CS0 thru CS5) so that in theory 6 different devices can be connected.
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
[all …]
/freebsd/usr.bin/clang/llvm-mca/
H A Dllvm-mca.14 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
19 . nr rst2man-indent-level +1
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A Dfrontend.json9 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
14 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
20 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
27 "Counter": "0,1,2,3,4,5,6,7",
33 "PEBScounters": "0,1,2,3,4,5,6,7",
34 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
42 "Counter": "0,1,2,3,4,5,6,7",
48 "PEBScounters": "0,1,2,3,4,5,6,7",
49 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
57 "Counter": "0,1,2,3,4,5,6,7",
[all …]

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