Lines Matching +full:cycle +full:- +full:6
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "CounterHTOff": "0,1,2,3,4,5,6,7",
53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB…
55 "CounterHTOff": "0,1,2,3,4,5,6,7",
58 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL…
65 "CounterHTOff": "0,1,2,3,4,5,6,7",
75 "CounterHTOff": "0,1,2,3,4,5,6,7",
86 "CounterHTOff": "0,1,2,3,4,5,6,7",
97 "CounterHTOff": "0,1,2,3,4,5,6,7",
108 "CounterHTOff": "0,1,2,3,4,5,6,7",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
130 "CounterHTOff": "0,1,2,3,4,5,6,7",
133 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = …
150 "CounterHTOff": "0,1,2,3,4,5,6,7",
160 "CounterHTOff": "0,1,2,3,4,5,6,7",
171 "CounterHTOff": "0,1,2,3,4,5,6,7",
174 …"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = …
181 "CounterHTOff": "0,1,2,3,4,5,6,7",
192 "CounterHTOff": "0,1,2,3,4,5,6,7",
203 "CounterHTOff": "0,1,2,3,4,5,6,7",
215 "CounterHTOff": "0,1,2,3,4,5,6,7",
218 …"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cma…
225 "CounterHTOff": "0,1,2,3,4,5,6,7",
228 …"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cm…
235 "CounterHTOff": "0,1,2,3,4,5,6,7",
247 "CounterHTOff": "0,1,2,3,4,5,6,7",
250 …"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MIT…
260 …ts where no uop was delivered from the front end to the back end when there is no back-end stall.",