Lines Matching +full:cycle +full:- +full:6

1 //===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14   let IssueWidth = 6;  // 4 (non-branch) instructions are dispatched per cycle.
15                        // Note that the dispatch bundle size is 6 (including
17                        // cycle (from all queues) is 8.
44   // Implemented as two 2-way SIMD operations for double- and single-precision.
53   // Executing simple FX, complex FX, permute and 4-way SIMD single-precision FP ops
83   def P7_CRU_6C : SchedWriteRes<[P7_CRU]> { let Latency = 6; }
97   def P7_VectorFPU_6C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 6; }
102   def P7_ScalarFPU_6C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 6; }