Lines Matching +full:cycle +full:- +full:6

1 //===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
15   // fetched from the instruction cache. However, only 6 instructions may be
21   // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
22   // However it is not worth bumping this value up to 6 when the vast majority
30   // A dispatch group is 6 instructions.
36   // 11-entry iop issue queue.
133   // Dispatch Rules: '-' or 'V'
134   // Vector ('V') - vector iops (128-bit operand) take only one decode and
142   // Even slice ('E')- certain operations must be sent only to an even slice.
149   // Paired ('P') - certain cracked and expanded iops are paired such that they
155   // Tuple Restricted ('R') - certain iops preclude dispatching more than one
156   // operation per slice for the super- slice to which they are dispatched
161   // Each execution and branch slice can receive up to two iops per cycle
192   // However, the ALU unit is only ever busy for 1 cycle at a time and may
193   // receive new instructions each cycle.
324   // Three cycle permute operations.
330   // Loads can have 4, 5 or 6 cycles of latency.
331   // Stores are listed as having a single cycle of latency. This is not
332   // completely accurate since it takes more than 1 cycle to actually store
334   // considered complete after one cycle.
348     let Latency = 6;
384   // 2 or 5 cycle latencies for the branch unit.
393   // 6 cycle latency for the crypto unit
395     let Latency = 6;