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/linux/Documentation/devicetree/bindings/gpio/
H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST Microelectronics SPEAr SPI CS GPIO Controller
10 - Viresh Kumar <vireshk@kernel.org>
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
37 st-spics,peripcfg-reg:
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H A Dfairchild,74hc595.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
11 have a rising-edge triggered latch clock (or storage register clock) pin,
12 which behaves like an active-low chip select.
14 After the bits are shifted into the shift register, CS# is driven high, which
16 transfer of the bits from the shift register to the storage register and thus
19 shift clock ____| |_| |_..._| |_| |_________
27 - Maxime Ripard <mripard@kernel.org>
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/linux/include/linux/
H A Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
44 * @shift: Cycle to nanosecond divisor (power of two)
49 * @archdata: Optional arch-specific data
60 * 1-99: Unfit for real use
62 * 100-199: Base level usability.
64 * 200-299: Good.
66 * 300-399: Desired.
68 * 400-499: Perfect
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/linux/drivers/bus/
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
43 * Inserted when reading one CS and switching to another CS or read
44 * followed by write on the same CS. Valid values 0 thru 15.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
47 * asserted until CS is asserted. With a hold of 1, the CS stays
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
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H A Dintel-ixp4xx-eb.c1 // SPDX-License-Identifier: GPL-2.0-only
32 /* Bits inside each CS timing register */
88 u16 shift; member
93 .prop = "intel,ixp4xx-eb-t1",
96 .shift = IXP4XX_EXP_T1_SHIFT,
99 .prop = "intel,ixp4xx-eb-t2",
102 .shift = IXP4XX_EXP_T2_SHIFT,
105 .prop = "intel,ixp4xx-eb-t3",
108 .shift = IXP4XX_EXP_T3_SHIFT,
111 .prop = "intel,ixp4xx-eb-t4",
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/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
23 static void clocksource_enqueue(struct clocksource *cs);
25 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
27 u64 delta = clocksource_delta(end, start, cs->mask, cs->max_raw_delta); in cycles_to_nsec_safe()
29 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
30 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
32 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
36 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
38 * @shift: pointer to shift variable
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H A Dtimekeeping.c1 // SPDX-License-Identifier: GPL-2.0
31 #include "tick-internal.h"
67 return ktime_get_aux_ts64(CLOCK_AUX + tkid - TIMEKEEPER_AUX_FIRST, ts); in tk_get_aux_ts64()
72 return tk->id >= TIMEKEEPER_AUX_FIRST && tk->id <= TIMEKEEPER_AUX_LAST; in tk_is_aux()
88 tk->offs_aux = offs; in tk_update_aux_offs()
89 tk->monotonic_to_aux = ktime_to_timespec64(offs); in tk_update_aux_offs()
96 * struct tk_fast - NMI safe timekeeper
109 /* Suspend-time cycles value for halted fast timekeeper. */
112 static u64 dummy_clock_read(struct clocksource *cs) in dummy_clock_read() argument
127 * and shift=0. When the first proper clocksource is installed then
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/linux/drivers/spi/
H A Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 /*----------------------------------------------------------------------*/
25 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
26 * Use this for GPIO or shift-register level hardware APIs.
28 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
30 * used, though maybe they're called from controller-aware code.
32 * chipselect() and friends may use spi_device->controller_data and
58 unsigned int bits = t->bits_per_word; in bitbang_txrx_8()
59 unsigned int count = t->len; in bitbang_txrx_8()
60 const u8 *tx = t->tx_buf; in bitbang_txrx_8()
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H A Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
58 if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN) in dw_spi_bt1_dirmap_create()
59 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
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H A Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi-mem.h>
23 #include "spi-dw.h"
66 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
67 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
69 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
71 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
72 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset); in dw_spi_debugfs_init()
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H A Dspi-cadence-quadspi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
73 u8 cs; member
324 if (ret != -ETIMEDOUT) in cqspi_wait_for_bit()
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/linux/drivers/gpio/
H A Dgpio-spear-spics.c1 // SPDX-License-Identifier: GPL-2.0-only
21 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
31 * struct spear_spics - represents spi chip select control
34 * @sw_enable_bit: bit to enable s/w control over chipselects
38 * @use_count: use count of a spi controller cs lines
61 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value()
62 if (spics->last_off != offset) { in spics_set_value()
63 spics->last_off = offset; in spics_set_value()
64 tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift); in spics_set_value()
65 tmp |= offset << spics->cs_enable_shift; in spics_set_value()
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/linux/arch/mips/loongson64/
H A Dhpet.c1 // SPDX-License-Identifier: GPL-2.0
82 /* Do nothing on Loongson-3 */ in hpet_enable_legacy_int()
139 * 0 : non-periodic(oneshot) interrupt in hpet_set_state_oneshot()
168 res = (s32)(cnt - hpet_read(HPET_COUNTER)); in hpet_next_event()
170 return res < HPET_MIN_CYCLES ? -ETIME : 0; in hpet_next_event()
184 cd->event_handler(cd); in hpet_irq_handler()
210 /* enable decoding of access to HPET MMIO*/ in hpet_setup()
213 /* HPET irq enable */ in hpet_setup()
228 cd->name = "hpet"; in setup_hpet_timer()
229 cd->rating = 100; in setup_hpet_timer()
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/linux/drivers/edac/
H A Damd64_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * cleared to prevent re-enabling the hardware by this driver.
21 if (!pvt->flags.zn_regs_v2) in get_umc_reg()
33 /* Per-node stuff */
41 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
83 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
96 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
108 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg); in f15h_select_dct()
109 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
111 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
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/linux/arch/arm/boot/dts/st/
H A Dspear1340.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spics,sw-enable-bit = <21>;
20 st-spics,cs-value-bit = <20>;
21 st-spics,cs-enable-mask = <3>;
22 st-spics,cs-enable-shift = <18>;
23 gpio-controller;
24 #gpio-cells = <2>;
29 compatible = "st,spear1340-miphy";
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H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
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/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
207 /* Structure to save gpmc cs context */
258 /* Define chip-selects as reserved by default until probe completes */
278 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
282 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
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/linux/drivers/clocksource/
H A Dsh_cmt.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
106 struct clocksource cs; member
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H A Dtimer-atmel-pit.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
5 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
23 #define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */
73 static u64 read_pit_clk(struct clocksource *cs) in read_pit_clk() argument
75 struct pit_data *data = clksrc_to_pit_data(cs); in read_pit_clk()
81 elapsed = data->cnt; in read_pit_clk()
82 t = pit_read(data->base, AT91_PIT_PIIR); in read_pit_clk()
85 elapsed += PIT_PICNT(t) * data->cycle; in read_pit_clk()
95 pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN); in pit_clkevt_shutdown()
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H A Dscx200_hrt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * high-resolution timer. The Geode SC-1100 (at least) has a buggy
8 * given as a boot-arg. In its absence, the Generic Timekeeping code
9 * will detect and de-rate the bad TSC, allowing this timer to take
12 * Based on work by John Stultz, and Ted Phelps (in a 2.6.12-rc6 patch)
29 MODULE_PARM_DESC(ppm, "+-adjust to actual XO freq (ppm)");
35 #define HR_TMEN (1 << 0) /* timer interrupt enable */
37 #define HR_TM27MPD (1 << 2) /* 1 turns off input clock (power-down) */
42 static u64 read_hrt(struct clocksource *cs) in read_hrt() argument
54 /* mult, shift are set based on mhz27 flag */
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/linux/drivers/mtd/nand/raw/
H A Dnuvoton-ma35d1-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/dma-mapping.h>
119 return -ERANGE; in ma35_ooblayout_ecc()
121 oob_region->length = chip->ecc.total; in ma35_ooblayout_ecc()
122 oob_region->offset = mtd->oobsize - oob_region->length; in ma35_ooblayout_ecc()
133 return -ERANGE; in ma35_ooblayout_free()
135 oob_region->length = mtd->oobsize - chip->ecc.total - 2; in ma35_ooblayout_free()
136 oob_region->offset = 2; in ma35_ooblayout_free()
152 writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0); in ma35_clear_spare()
158 u32 value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset); in read_remaining_bytes()
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/linux/drivers/iio/adc/
H A Dad4695.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/iio/buffer-dmaengine.h>
38 #include <dt-bindings/iio/adc/adi,ad4695.h>
157 * to control CS and add a delay between the last SCLK and next
208 .name = "ad4695-8",
237 .name = "ad4695-16",
254 .tx_buf = st->regmap_bus_data, in ad4695_regmap_bus_reg_write()
257 if (count > ARRAY_SIZE(st->regmap_bus_data)) in ad4695_regmap_bus_reg_write()
258 return -EINVAL; in ad4695_regmap_bus_reg_write()
260 memcpy(st->regmap_bus_data, data, count); in ad4695_regmap_bus_reg_write()
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/linux/arch/microblaze/kernel/
H A Dtimer.c2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
88 * !ENALL - don't enable 'em all in xilinx_timer0_start_periodic()
89 * !PWMA - disable pwm in xilinx_timer0_start_periodic()
90 * TINT - clear interrupt status in xilinx_timer0_start_periodic()
91 * ENT- enable timer itself in xilinx_timer0_start_periodic()
92 * ENIT - enable interrupt in xilinx_timer0_start_periodic()
93 * !LOAD - clear the bit to let go in xilinx_timer0_start_periodic()
94 * ARHT - auto reload in xilinx_timer0_start_periodic()
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/linux/drivers/ps3/
H A Dps3av_cmd.c1 // SPDX-License-Identifier: GPL-2.0-only
28 int cs; member
33 .cs = PS3AV_CMD_VIDEO_CS_RGB_8,
37 .cs = PS3AV_CMD_VIDEO_CS_RGB_10,
41 .cs = PS3AV_CMD_VIDEO_CS_RGB_12,
45 .cs = PS3AV_CMD_VIDEO_CS_YUV444_8,
49 .cs = PS3AV_CMD_VIDEO_CS_YUV444_10,
53 .cs = PS3AV_CMD_VIDEO_CS_YUV444_12,
57 .cs = PS3AV_CMD_VIDEO_CS_YUV422_8,
61 .cs = PS3AV_CMD_VIDEO_CS_YUV422_10,
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/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
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