Lines Matching +full:cs +full:- +full:enable +full:- +full:shift
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
11 have a rising-edge triggered latch clock (or storage register clock) pin,
12 which behaves like an active-low chip select.
14 After the bits are shifted into the shift register, CS# is driven high, which
16 transfer of the bits from the shift register to the storage register and thus
19 shift clock ____| |_| |_..._| |_| |_________
27 - Maxime Ripard <mripard@kernel.org>
32 - fairchild,74hc595
33 - nxp,74lvc594
38 gpio-controller: true
40 '#gpio-cells':
45 registers-number:
47 description: Number of daisy-chained shift registers
49 enable-gpios:
50 description: GPIO connected to the OE (Output Enable) pin.
54 "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
57 - gpio-hog
60 - compatible
61 - reg
62 - gpio-controller
63 - '#gpio-cells'
64 - registers-number
67 - $ref: /schemas/spi/spi-peripheral-props.yaml#
72 - |
74 #address-cells = <1>;
75 #size-cells = <0>;
80 gpio-controller;
81 #gpio-cells = <2>;
82 registers-number = <4>;
83 spi-max-frequency = <100000>;