1 // SPDX-License-Identifier: GPL-2.0-only
3  * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
5  * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
23 #define AT91_PIT_PITIEN			BIT(25)			/* Timer Interrupt Enable */
73 static u64 read_pit_clk(struct clocksource *cs)  in read_pit_clk()  argument
75 	struct pit_data *data = clksrc_to_pit_data(cs);  in read_pit_clk()
81 	elapsed = data->cnt;  in read_pit_clk()
82 	t = pit_read(data->base, AT91_PIT_PIIR);  in read_pit_clk()
85 	elapsed += PIT_PICNT(t) * data->cycle;  in read_pit_clk()
95 	pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN);  in pit_clkevt_shutdown()
107 	data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));  in pit_clkevt_set_periodic()
108 	pit_write(data->base, AT91_PIT_MR,  in pit_clkevt_set_periodic()
109 		  (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN);  in pit_clkevt_set_periodic()
118 	pit_write(data->base, AT91_PIT_MR, 0);  in at91sam926x_pit_suspend()
124 	pit_write(data->base, AT91_PIT_MR, 0);  in at91sam926x_pit_reset()
127 	while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)  in at91sam926x_pit_reset()
130 	/* Start PIT but don't enable IRQ */  in at91sam926x_pit_reset()
131 	pit_write(data->base, AT91_PIT_MR,  in at91sam926x_pit_reset()
132 		  (data->cycle - 1) | AT91_PIT_PITEN);  in at91sam926x_pit_reset()
150 	if (clockevent_state_periodic(&data->clkevt) &&  in at91sam926x_pit_interrupt()
151 	    (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {  in at91sam926x_pit_interrupt()
153 		data->cnt += data->cycle * PIT_PICNT(pit_read(data->base,  in at91sam926x_pit_interrupt()
155 		data->clkevt.event_handler(&data->clkevt);  in at91sam926x_pit_interrupt()
175 		return -ENOMEM;  in at91sam926x_pit_dt_init()
177 	data->base = of_iomap(node, 0);  in at91sam926x_pit_dt_init()
178 	if (!data->base) {  in at91sam926x_pit_dt_init()
180 		ret = -ENXIO;  in at91sam926x_pit_dt_init()
184 	data->mck = of_clk_get(node, 0);  in at91sam926x_pit_dt_init()
185 	if (IS_ERR(data->mck)) {  in at91sam926x_pit_dt_init()
187 		ret = PTR_ERR(data->mck);  in at91sam926x_pit_dt_init()
191 	ret = clk_prepare_enable(data->mck);  in at91sam926x_pit_dt_init()
193 		pr_err("Unable to enable mck\n");  in at91sam926x_pit_dt_init()
198 	data->irq = irq_of_parse_and_map(node, 0);  in at91sam926x_pit_dt_init()
199 	if (!data->irq) {  in at91sam926x_pit_dt_init()
201 		ret = -EINVAL;  in at91sam926x_pit_dt_init()
207 	 * 1/HZ period (instead of a compile-time constant LATCH).  in at91sam926x_pit_dt_init()
209 	pit_rate = clk_get_rate(data->mck) / 16;  in at91sam926x_pit_dt_init()
210 	data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);  in at91sam926x_pit_dt_init()
211 	WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);  in at91sam926x_pit_dt_init()
213 	/* Initialize and enable the timer */  in at91sam926x_pit_dt_init()
218 	 * so this isn't a 32-bit counter unless we get clockevent irqs.  in at91sam926x_pit_dt_init()
220 	bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */;  in at91sam926x_pit_dt_init()
221 	data->clksrc.mask = CLOCKSOURCE_MASK(bits);  in at91sam926x_pit_dt_init()
222 	data->clksrc.name = "pit";  in at91sam926x_pit_dt_init()
223 	data->clksrc.rating = 175;  in at91sam926x_pit_dt_init()
224 	data->clksrc.read = read_pit_clk;  in at91sam926x_pit_dt_init()
225 	data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;  in at91sam926x_pit_dt_init()
227 	ret = clocksource_register_hz(&data->clksrc, pit_rate);  in at91sam926x_pit_dt_init()
234 	ret = request_irq(data->irq, at91sam926x_pit_interrupt,  in at91sam926x_pit_dt_init()
239 		clocksource_unregister(&data->clksrc);  in at91sam926x_pit_dt_init()
244 	data->clkevt.name = "pit";  in at91sam926x_pit_dt_init()
245 	data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;  in at91sam926x_pit_dt_init()
246 	data->clkevt.shift = 32;  in at91sam926x_pit_dt_init()
247 	data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);  in at91sam926x_pit_dt_init()
248 	data->clkevt.rating = 100;  in at91sam926x_pit_dt_init()
249 	data->clkevt.cpumask = cpumask_of(0);  in at91sam926x_pit_dt_init()
251 	data->clkevt.set_state_shutdown = pit_clkevt_shutdown;  in at91sam926x_pit_dt_init()
252 	data->clkevt.set_state_periodic = pit_clkevt_set_periodic;  in at91sam926x_pit_dt_init()
253 	data->clkevt.resume = at91sam926x_pit_resume;  in at91sam926x_pit_dt_init()
254 	data->clkevt.suspend = at91sam926x_pit_suspend;  in at91sam926x_pit_dt_init()
255 	clockevents_register_device(&data->clkevt);  in at91sam926x_pit_dt_init()
263 TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",