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Searched +full:crystal +full:- +full:freq (Results 1 – 25 of 50) sorted by relevance

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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dpllnv04.c2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2007-2009 Stuart Bennett
40 struct nvkm_bios *bios = subdev->device->bios; in getMNP_single()
41 int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq; in getMNP_single()
42 int minM = info->vco1.min_m, maxM = info->vco1.max_m; in getMNP_single()
43 int minN = info->vco1.min_n, maxN = info->vco1.max_n; in getMNP_single()
44 int minU = info->vco1.min_inputfreq; in getMNP_single()
45 int maxU = info->vco1.max_inputfreq; in getMNP_single()
46 int minP = info->min_p; in getMNP_single()
47 int maxP = info->max_p_usable; in getMNP_single()
[all …]
H A Dgf100.c33 u32 freq; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
107 return device->crystal; in read_div()
[all …]
H A Dgk104.c33 u32 freq; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
77 sclk = device->crystal; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
147 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
192 struct nvkm_subdev *subdev = &clk->base.subdev; in gk104_clk_read()
193 struct nvkm_device *device = subdev->device; in gk104_clk_read()
[all …]
H A Dnv50.c34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll_src()
127 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_ref()
128 struct nvkm_device *device = subdev->device; in read_pll_ref()
[all …]
/linux/drivers/media/radio/
H A Dtea575x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <media/v4l2-device.h>
15 #include <media/v4l2-dev.h>
16 #include <media/v4l2-fh.h>
17 #include <media/v4l2-ioctl.h>
18 #include <media/v4l2-event.h>
19 #include <media/drv-intf/tea575x.h>
87 if (tea->ops->write_val) in snd_tea575x_write()
88 return tea->ops->write_val(tea, val); in snd_tea575x_write()
90 tea->ops->set_direction(tea, 1); in snd_tea575x_write()
[all …]
/linux/arch/x86/kernel/
H A Dtsc_msr.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <asm/intel-family.h>
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
63 * so the freq number is not exactly the same as reported
138 * 24 MHz crystal? : 24 * 13 / 4 = 78 MHz
161 * MSR-based CPU/TSC frequency discovery for certain CPUs.
168 u32 lo, hi, ratio, freq, tscref; in cpu_khz_from_msr() local
179 freq_desc = (struct freq_desc *)id->driver_data; in cpu_khz_from_msr()
180 if (freq_desc->use_msr_plat) { in cpu_khz_from_msr()
188 /* Get FSB FREQ ID */ in cpu_khz_from_msr()
[all …]
H A Dtsc.c1 // SPDX-License-Identifier: GPL-2.0-only
81 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset); in __cyc2ns_read()
82 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul); in __cyc2ns_read()
83 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift); in __cyc2ns_read()
103 * ns = cycles / (freq / ns_per_sec)
104 * ns = cycles * (ns_per_sec / freq)
114 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
115 * (64-bit result) can be used.
120 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
164 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit in __set_cyc2ns_scale()
[all …]
/linux/drivers/ssb/
H A Ddriver_chipcommon_pmu.c51 u16 freq; /* Crystal frequency in kHz.*/ member
52 u8 xf; /* Crystal frequency value for PMU control */
58 { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
59 { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
60 { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
61 { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
62 { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
63 { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
64 { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
65 { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
[all …]
/linux/drivers/media/pci/cx18/
H A Dcx18-av-audio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from cx25840-audio.c
11 #include "cx18-driver.h"
13 static int set_audclk_freq(struct cx18 *cx, u32 freq) in set_audclk_freq() argument
15 struct cx18_av_state *state = &cx->av_state; in set_audclk_freq()
17 if (freq != 32000 && freq != 44100 && freq != 48000) in set_audclk_freq()
18 return -EINVAL; in set_audclk_freq()
21 * The PLL parameters are based on the external crystal frequency that in set_audclk_freq()
24 * NTSC Color subcarrier freq * 8 = in set_audclk_freq()
31 * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80 in set_audclk_freq()
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H A Dcx18-firmware.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "cx18-driver.h"
10 #include "cx18-io.h"
11 #include "cx18-scb.h"
12 #include "cx18-irq.h"
13 #include "cx18-firmware.h"
14 #include "cx18-cards.h"
95 if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { in load_cpu_fw_direct()
98 return -ENOMEM; in load_cpu_fw_direct()
101 src = (const u32 *)fw->data; in load_cpu_fw_direct()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dcs43130.txt5 - compatible : "cirrus,cs43130", "cirrus,cs4399", "cirrus,cs43131",
8 - reg : the I2C address of the device for I2C
10 - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
17 - reset-gpios : Active low GPIO used to reset the device
19 - cirrus,xtal-ibias:
20 When external MCLK is generated by external crystal
22 for external crystal. Amount of bias current sent is
28 - cirrus,dc-measure:
31 - cirrus,ac-measure:
35 - cirrus,dc-threshold:
[all …]
/linux/drivers/clk/
H A Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_gate_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
77 * struct gemini_reset - gemini reset controller
90 { 1, "security-gate", "secdiv", 0 },
[all …]
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
[all …]
H A Dclk-tps68470.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/clk-provider.h>
26 #define TPS68470_CLK_NAME "tps68470-clk"
32 unsigned long freq; member
40 * The PLL is used to multiply the crystal oscillator
80 if (regmap_read(clkdata->regmap, TPS68470_REG_PLLCTL, &val)) in tps68470_clk_is_prepared()
90 regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1, in tps68470_clk_prepare()
94 regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL, in tps68470_clk_prepare()
111 regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL, TPS68470_PLL_EN_MASK, 0); in tps68470_clk_unprepare()
113 /* ... and then tri-state the clock outputs. */ in tps68470_clk_unprepare()
[all …]
/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
91 * Controller (UDC) Control/Status register end-point 0
94 * Controller (UDC) Control/Status register end-point 1
97 * Controller (UDC) Control/Status register end-point 2
100 * Controller (UDC) Data register end-point 0
[all …]
/linux/drivers/rtc/
H A Drtc-stmp3xxx.c1 // SPDX-License-Identifier: GPL-2.0+
64 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
82 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG); in stmp3xxx_wdt_set_timeout()
84 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); in stmp3xxx_wdt_set_timeout()
86 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET); in stmp3xxx_wdt_set_timeout()
89 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_wdt_set_timeout()
91 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR); in stmp3xxx_wdt_set_timeout()
101 int rc = -1; in stmp3xxx_wdt_register()
103 platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id); in stmp3xxx_wdt_register()
106 wdt_pdev->dev.parent = &rtc_pdev->dev; in stmp3xxx_wdt_register()
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_led.c39 struct drm_device *drm_dev = container_of(led, struct nouveau_led, led)->dev; in nouveau_led_get_brightness()
41 struct nvif_object *device = &drm->client.device.object; in nouveau_led_get_brightness()
56 struct drm_device *drm_dev = container_of(led, struct nouveau_led, led)->dev; in nouveau_led_set_brightness()
58 struct nvif_object *device = &drm->client.device.object; in nouveau_led_set_brightness()
60 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ in nouveau_led_set_brightness()
61 u32 freq = 100; /* this is what nvidia uses and it should be good-enough */ in nouveau_led_set_brightness() local
64 div = input_clk / freq; in nouveau_led_set_brightness()
68 * - A: nvidia never puts the logo led to any other PWM controler in nouveau_led_set_brightness()
70 * - B: nouveau does not touch these registers anywhere else in nouveau_led_set_brightness()
92 drm->led = kzalloc(sizeof(*drm->led), GFP_KERNEL); in nouveau_led_init()
[all …]
/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
158 #define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
164 …NXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate …
165 #define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
225 #define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
395 /** Chip specific Chip-Status register contents. */
410 /** Macros to determine SPROM presence based on Chip-Status register. */
444 #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
[all …]
/linux/include/linux/mfd/
H A Dsi476x-platform.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/media/si476x-platform.h -- Platform data specific definitions
185 * @xcload: Selects the amount of additional on-chip capacitance to
197 * SI476X_BOOTLOADER - Boot loader
198 * SI476X_FM_RECEIVER - FM receiver
199 * SI476X_AM_RECEIVER - AM receiver
200 * SI476X_WB_RECEIVER - Weatherband receiver
201 * @freq: oscillator's crystal frequency:
202 * SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
203 * SI476X_XTAL_36P4_MHZ - 36.4 Mhz
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dpmu.c29 * external LPO crystal frequency
55 /* ALP clock on pre-PMU chips */
128 core = sii->icbus->drv_cc.core; in si_pmu_measure_alpclk()
134 * Enable the reg to measure the freq, in si_pmu_measure_alpclk()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgk104.c99 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
149 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { in gk104_ram_train()
150 if (ram->pmask & (1 << i)) in gk104_ram_train()
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); in r1373f4_init()
161 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); in r1373f4_init()
162 const u32 runk0 = ram->fN1 << 16; in r1373f4_init()
163 const u32 runk1 = ram->fN1; in r1373f4_init()
165 if (ram->from == 2) { in r1373f4_init()
191 if (ram->mode == 2) { in r1373f4_init()
210 struct nvkm_ram_data *next = ram->base.next; in r1373f4_fini()
[all …]
/linux/drivers/irqchip/
H A Dirq-bcm2836.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <linux/irqchip/irq-bcm2836.h>
46 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_mask_timer_irq()
53 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_unmask_timer_irq()
58 .name = "bcm2836-timer",
75 .name = "bcm2836-pmu",
90 .name = "bcm2836-gpu",
101 .name = "bcm2836-dummy",
128 return -EINVAL; in bcm2836_map()
132 irq_domain_set_info(d, irq, hw, chip, d->host_data, in bcm2836_map()
[all …]
/linux/drivers/net/can/sja1000/
H A Dtscan1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * tscan1.c: driver for Technologic Systems TS-CAN1 PC104 boards
9 * - Getting started with TS-CAN1, Technologic Systems, Feb 2022
10 * https://docs.embeddedts.com/TS-CAN1
21 MODULE_DESCRIPTION("Driver for Technologic Systems TS-CAN1 PC104 boards");
57 /* SJA1000 crystal frequency (16MHz) */
68 return inb((unsigned long)priv->reg_base + reg); in tscan1_read()
74 outb(val, (unsigned long)priv->reg_base + reg); in tscan1_write()
77 /* Probe for a TS-CAN1 board with JP2:JP1 jumper setting ID */
87 return -EBUSY; in tscan1_probe()
[all …]
/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kalle Valo <kvalo@kernel.org>
11 - Jeff Johnson <jjohnson@kernel.org>
19 - qcom,ath10k # SDIO-based devices
20 - qcom,ipq4019-wifi
21 - qcom,wcn3990-wifi # SNoC-based devices
26 reg-names:
28 - const: membase
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/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
154 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
157 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
232 #define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
238 …NXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate …
239 #define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
[all …]

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