1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "cx18-driver.h"
10 #include "cx18-io.h"
11 #include "cx18-scb.h"
12 #include "cx18-irq.h"
13 #include "cx18-firmware.h"
14 #include "cx18-cards.h"
95 	if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {  in load_cpu_fw_direct()
98 		return -ENOMEM;  in load_cpu_fw_direct()
101 	src = (const u32 *)fw->data;  in load_cpu_fw_direct()
103 	for (i = 0; i < fw->size; i += 4096) {  in load_cpu_fw_direct()
105 		for (j = i; j < fw->size && j < i + 4096; j += 4) {  in load_cpu_fw_direct()
112 				return -EIO;  in load_cpu_fw_direct()
118 	if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))  in load_cpu_fw_direct()
119 		CX18_INFO("loaded %s firmware (%zu bytes)\n", fn, fw->size);  in load_cpu_fw_direct()
120 	size = fw->size;  in load_cpu_fw_direct()
139 	if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {  in load_apu_fw_direct()
143 		return -ENOMEM;  in load_apu_fw_direct()
147 	src = (const u32 *)fw->data;  in load_apu_fw_direct()
148 	vers = fw->data + sizeof(seghdr);  in load_apu_fw_direct()
149 	sz = fw->size;  in load_apu_fw_direct()
152 	while (offset + sizeof(seghdr) < fw->size) {  in load_apu_fw_direct()
166 		CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,  in load_apu_fw_direct()
167 				seghdr.addr + seghdr.size - 1);  in load_apu_fw_direct()
184 					return -EIO;  in load_apu_fw_direct()
190 	if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))  in load_apu_fw_direct()
192 				fn, apu_version, fw->size);  in load_apu_fw_direct()
193 	size = fw->size;  in load_apu_fw_direct()
210 	/* power-down Spare and AOM PLLs */  in cx18_init_power()
211 	/* power-up fast, slow and mpeg PLLs */  in cx18_init_power()
219 	 * The PLL parameters are based on the external crystal frequency that  in cx18_init_power()
222 	 * NTSC Color subcarrier freq * 8 =  in cx18_init_power()
229 	 * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80  in cx18_init_power()
232 	 * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83  in cx18_init_power()
234 	 * As Mike Bradley has rightly pointed out, it's not the exact crystal  in cx18_init_power()
239 	 * crystal value at all, it will assume 28.636360 MHz, the crystal  in cx18_init_power()
240 	 * freq used in calculations in this driver will be:  in cx18_init_power()
245 	 * the shelf crystal will have for accuracy anyway.  in cx18_init_power()
255 	/* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/  in cx18_init_power()
256 	/* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/  in cx18_init_power()
266 	/* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */  in cx18_init_power()
267 	/* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */  in cx18_init_power()
274 	/* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */  in cx18_init_power()
324 	cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);  in cx18_init_memory()
328 	cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);  in cx18_init_memory()
329 	cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);  in cx18_init_memory()
330 	cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);  in cx18_init_memory()
335 	cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);  in cx18_init_memory()
336 	cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);  in cx18_init_memory()
344 	/* use power-down mode when idle */  in cx18_init_memory()
365 #define CX18_CPU_FIRMWARE "v4l-cx23418-cpu.fw"
366 #define CX18_APU_FIRMWARE "v4l-cx23418-apu.fw"
386 		return -EIO;  in cx18_firmware_init()
392 	sz = load_cpu_fw_direct(CX18_CPU_FIRMWARE, cx->enc_mem, cx);  in cx18_firmware_init()
400 	sz = load_apu_fw_direct(CX18_APU_FIRMWARE, cx->enc_mem, cx,  in cx18_firmware_init()
420 		return -EIO;  in cx18_firmware_init()