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/linux/Documentation/devicetree/bindings/clock/ti/
H A Dcomposite.txt1 Binding for TI composite clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped composite clock with multiple different sub-types;
6 a multiplexer clock with multiple input clock signals or parents, one
9 an adjustable clock rate divider, this behaves exactly as [3]
12 clock, this behaves exactly as [4]
15 merged to this clock. The component clocks shall be of one of the
16 "ti,*composite*-clock" types.
18 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
19 [2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
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H A Dti,divider-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments divider clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
14 that does not gate and has only one input clock or parent. By default the
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
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H A Dti,mux-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments mux clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
14 signals or parents, one of which can be selected as output. This clock does
15 not gate or adjust the parent rate via a divider or multiplier.
24 register value selected parent clock
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/linux/arch/arm/boot/dts/ti/omap/
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
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H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
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H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
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H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
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H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2420 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
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H A Domap3430es1-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3430 ES1 clock data
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
20 ti,max-div = <7>;
22 ti,index-starts-at-one;
26 #clock-cells = <0>;
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H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2430 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
31 #clock-cells = <0>;
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H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
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H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
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/linux/drivers/clk/stm32/
H A Dclk-stm32-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
17 #include "clk-stm32-core.h"
18 #include "reset-stm32.h"
26 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_clock_init()
27 struct clk_hw_onecell_data *clk_data = data->hw_clks; in stm32_rcc_clock_init()
31 max_binding = data->maxbinding; in stm32_rcc_clock_init()
35 return -ENOMEM; in stm32_rcc_clock_init()
37 clk_data->num = max_binding; in stm32_rcc_clock_init()
39 hws = clk_data->hws; in stm32_rcc_clock_init()
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/linux/drivers/clk/ti/
H A Dcomposite.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI composite clock support
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
18 #include "clock.h"
32 return -EINVAL; in ti_composite_round_rate()
38 return -EINVAL; in ti_composite_set_rate()
63 "gate", "divider", "mux"
73 rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i, in _get_component_node()
86 if (comp->node == node) in _lookup_component()
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H A Dgate.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP gate clock support
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
17 #include "clock.h"
48 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
74 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
78 dummy_v ^= (1 << parent->shift); in omap36xx_gate_clk_enable_with_hsdiv_restore()
79 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
81 /* Write the original divider */ in omap36xx_gate_clk_enable_with_hsdiv_restore()
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H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Divider Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
16 #include "clock.h"
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
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/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,sai-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale SAI bitclock-as-a-clock
10 - Michael Walle <michael@walle.cc>
13 It is possible to use the BCLK pin of a SAI module as a generic clock
18 clock of the second SAI as a MCLK clock for an audio codec, for example.
20 This is a composite of a gated clock and a divider clock.
24 const: fsl,vf610-sai-clock
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/linux/drivers/clk/sunxi/
H A Dclk-sun9i-cpus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Allwinner A80 CPUS clock driver
12 #include <linux/clk-provider.h>
57 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
59 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
63 /* clk divider */ in sun9i_a80_cpus_clk_recalc_rate()
75 * clock can only divide, so we will never be able to achieve in sun9i_a80_cpus_clk_round()
83 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
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/linux/drivers/clk/berlin/
H A Dberlin2-div.c1 // SPDX-License-Identifier: GPL-2.0
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
9 #include <linux/clk-provider.h>
16 #include "berlin2-div.h"
19 * Clock dividers in Berlin2 SoCs comprise a complex cell to select
20 * input pll and divider. The virtual structure as it is used in Marvell
23 * +---+
24 * pll0 --------------->| 0 | +---+
25 * +---+ |(B)|--+--------------->| 0 | +---+
26 * pll1.0 -->| 0 | +-->| 1 | | +--------+ |(E)|----->| 0 | +---+
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/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
27 /* Clock registers on System Control Block */
60 /* Clock registers on USB controller */
85 /* Start from the last defined clock in dt bindings */
115 /* Two clock sources external to the driver */
127 /* Stub for composite clocks */
130 /* Subclocks of composite clocks, clocks above are for CCF */
252 * CLK_GET_RATE_NOCACHE is needed, if UART clock is disabled, its
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/linux/drivers/clk/mediatek/
H A Dclk-mtk.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
19 #include "clk-mtk.h"
20 #include "clk-gate.h"
21 #include "clk-mux.h"
44 clk_data->num = clk_num; in mtk_init_clk_data()
47 clk_data->hws[i] = ERR_PTR(-ENOENT); in mtk_init_clk_data()
93 return -ENOMEM; in mtk_clk_register_fixed_clks()
98 if (!IS_ERR_OR_NULL(clk_data->hws[rc->id])) { in mtk_clk_register_fixed_clks()
99 pr_warn("Trying to register duplicate clock ID: %d\n", rc->id); in mtk_clk_register_fixed_clks()
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/linux/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
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/linux/drivers/clk/actions/
H A Dowl-composite.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 // OWL composite clock driver
6 // Author: David Liu <liuwei@actions-semi.com>
14 #include "owl-common.h"
15 #include "owl-mux.h"
16 #include "owl-gate.h"
17 #include "owl-factor.h"
18 #include "owl-fixed-factor.h"
19 #include "owl-divider.h"
/linux/drivers/clk/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 # common clock types
3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_CLK_KUNIT_TEST) += clk-test.o
6 clk-test-y := clk_test.o \
22 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
23 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
24 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
25 obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) += clk-fixed-rate-test.o
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/linux/drivers/clk/rockchip/
H A Dclk-rk3368.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/rk3368-cru.h>
276 * Clock-Architecture Diagram 2
320 COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
356 COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
361 * but stclk_mcu has an additional own divider in diagram 2
367 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
379 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
388 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
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